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CSR Bit Fields

RISC-V minstret CSR Register

Address 0xB02Privilege MachineAccess RW / 64Machine counters and performance-monitoring CSRs

Machine instructions-retired counter; RW in M-mode, counts instructions retired by the hart.

Related Search Terms
minstret CSRminstret 0xB02machine instret counterretired instruction counterRDINSTRET sourcemcountinhibit IR
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
INSTRET63:0RW
Field Map

Understand minstret By Bit Fields

1 key fields
63:0

INSTRET

RW

Retired instruction count

INSTRET (bits 63:0) — Retired instruction count.

What This Field Controls

  • - Retired instruction count

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

minstret is the M-mode RW retired-instruction counter at 0xB02. It is 64 bits on RV32 and RV64 and counts instructions retired by the hart.

minstret address, lowest access privilege, and access class are checked against the official CSR table: 0xB02, Machine, RW.
minstret counts instructions retired by the hart, and its reset value is arbitrary.
mcountinhibit.IR controls whether minstret increments, not accessibility.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - minstret has 64-bit precision on all RV32 and RV64 harts; its reset value is arbitrary.
  • - On RV32, minstret reads the low 32 bits and minstreth reads bits 63:32.
  • - In S or U mode, reading instret raises an illegal-instruction exception when mcounteren.IR is zero; that setting does not stop the underlying counter.

Risk Checks Before Writing

  • - A CSR write takes effect after the writing instruction has otherwise completed.
  • - When mcountinhibit.IR is one, minstret stops incrementing; that setting does not change accessibility.

Put It Back Into A Real Flow

1

Read minstret in M-mode to obtain the current retired-instruction count.

2

On RV32, combine it with minstreth when reading the full 64-bit value.

3

Configure mcountinhibit.IR to stop incrementing; it affects incrementing, not accessibility.

FAQ

Can minstret be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records minstret as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing minstret?

A write takes effect after the writing CSR instruction has otherwise completed. Use mcountinhibit.IR to stop incrementing; it does not restrict CSR accessibility.