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CSR Bit Fields

RISC-V mcycle CSR Register

Address 0xB00Privilege MachineAccess RW / 64Machine counters and performance-monitoring CSRs

Machine cycle counter; RW in M-mode, counts clock cycles since the hart started running.

Related Search Terms
mcycle CSRmcycle 0xB00machine cycle countermcycle counterRDCYCLE sourcemcountinhibit CY
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
CYCLE63:0RW
Field Map

Understand mcycle By Bit Fields

1 key fields
63:0

CYCLE

RW

Cycle count value

CYCLE (bits 63:0) — Cycle count value.

What This Field Controls

  • - Cycle count value

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mcycle is a RW CSR in machine counters and performance-monitoring csrs at 0xB00. Check privilege and implemented extensions before interpreting its bit fields.

mcycle address, lowest access privilege, and access class are checked against the official CSR table: 0xB00, Machine, RW.
Read it as part of machine counters and performance-monitoring csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mcycle; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0xB00 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mcycle to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mcycle be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mcycle as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mcycle?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.