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CSR Bit Fields

RISC-V mcycle CSR Register

Address 0xB00Privilege MachineAccess RW / 64Machine counters and performance-monitoring CSRs

Machine cycle counter; RW in M-mode, counts clock cycles executed by the processor core on which the hart runs.

Related Search Terms
mcycle CSRmcycle 0xB00machine cycle countermcycle counterRDCYCLE sourcemcountinhibit CY
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
CYCLE63:0RW
Field Map

Understand mcycle By Bit Fields

1 key fields
63:0

CYCLE

RW

Cycle count value

CYCLE (bits 63:0) — Cycle count value.

What This Field Controls

  • - Cycle count value

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mcycle is the M-mode RW cycle counter at 0xB00. It is 64 bits on RV32 and RV64 and counts clock cycles executed by the hart's processor core.

mcycle address, lowest access privilege, and access class are checked against the official CSR table: 0xB00, Machine, RW.
mcycle counts clock cycles executed by the hart's processor core, and its reset value is arbitrary.
mcountinhibit.CY controls whether mcycle increments, not accessibility; harts on one core may share mcycle.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - mcycle has 64-bit precision on all RV32 and RV64 harts; its reset value is arbitrary.
  • - On RV32, mcycle reads the low 32 bits and mcycleh reads bits 63:32.
  • - In S or U mode, reading cycle raises an illegal-instruction exception when mcounteren.CY is zero; that setting does not stop the underlying counter.

Risk Checks Before Writing

  • - A CSR write takes effect after the writing instruction has otherwise completed.
  • - mcycle may be shared by harts on the same core; writes to a shared mcycle are visible to those harts.

Put It Back Into A Real Flow

1

Read mcycle in M-mode to obtain the current cycle count.

2

When writing it, account for the write taking effect after that CSR instruction completes.

3

Configure mcountinhibit.CY to stop incrementing; it affects incrementing, not accessibility.

FAQ

Can mcycle be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mcycle as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mcycle?

A write takes effect after the writing CSR instruction has otherwise completed. mcycle may be shared by harts on one core, so the write can be visible to those harts.