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CSR Bit Fields

RISC-V mcyclecfg CSR Register

Address 0x321Privilege MachineAccess RW / 64Machine counters and performance-monitoring CSRs

mcyclecfg at 0x321 is the Smcntrpmf machine counter-configuration CSR that filters mcycle counting by privilege mode.

Related Search Terms
mcyclecfg CSRmcyclecfg 0x321Smcntrpmfmcycle filteringprivilege mode countingxINH bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
ZERO63RO 0WPRI57:0WPRI
Field Map

Understand mcyclecfg By Bit Fields

7 key fields
63

ZERO

RO 0

Read-only zero at the OF position; mcyclecfg/minstretcfg do not generate local counter-overflow interrupts.

ZERO (bit 63) — Read-only zero at the OF position; mcyclecfg/minstretcfg do not generate local counter-overflow interrupts.

What This Field Controls

  • - Read-only zero at the OF position; mcyclecfg/minstretcfg do not generate local counter-overflow interrupts.

Common Values

mcyclecfg.ZERO
0Read-only zero

This bit corresponds to the Sscofpmf OF position, but Smcntrpmf defines it as read-only 0 for cycle/instret configuration; software must not write 1 or depend on a meaning for 1.

62

MINH

RW

When set, inhibits event counting in M-mode.

MINH (bit 62) — When set, inhibits event counting in M-mode.

What This Field Controls

  • - When set, inhibits event counting in M-mode.

Common Values

MINH mode-filter bit
0Counting allowed

cycle counting in M-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in M-mode is inhibited.

61

SINH

RW

When set, inhibits event counting in S/HS-mode; if the associated privilege mode is not implemented, this bit is read-only zero.

SINH (bit 61) — When set, inhibits event counting in S/HS-mode; if the associated privilege mode is not implemented, this bit is read-only zero.

What This Field Controls

  • - When set, inhibits event counting in S/HS-mode; if the associated privilege mode is not implemented, this bit is read-only zero.

Common Values

SINH mode-filter bit
0Counting allowed

cycle counting in S/HS-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in S/HS-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

60

UINH

RW

When set, inhibits event counting in U-mode; if U-mode is not implemented, this bit is read-only zero.

UINH (bit 60) — When set, inhibits event counting in U-mode; if U-mode is not implemented, this bit is read-only zero.

What This Field Controls

  • - When set, inhibits event counting in U-mode; if U-mode is not implemented, this bit is read-only zero.

Common Values

UINH mode-filter bit
0Counting allowed

cycle counting in U-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in U-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

59

VSINH

RW

When set, inhibits event counting in VS-mode; if Hypervisor/VS mode is not implemented, this bit is read-only zero.

VSINH (bit 59) — When set, inhibits event counting in VS-mode; if Hypervisor/VS mode is not implemented, this bit is read-only zero.

What This Field Controls

  • - When set, inhibits event counting in VS-mode; if Hypervisor/VS mode is not implemented, this bit is read-only zero.

Common Values

VSINH mode-filter bit
0Counting allowed

cycle counting in VS-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in VS-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

58

VUINH

RW

When set, inhibits event counting in VU-mode; if VU-mode is not implemented, this bit is read-only zero.

VUINH (bit 58) — When set, inhibits event counting in VU-mode; if VU-mode is not implemented, this bit is read-only zero.

What This Field Controls

  • - When set, inhibits event counting in VU-mode; if VU-mode is not implemented, this bit is read-only zero.

Common Values

VUINH mode-filter bit
0Counting allowed

cycle counting in VU-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in VU-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

57:0

WPRI

WPRI

Reserved writes-preserve-values fields; preserve these bits when writing other fields and do not rely on read values.

WPRI (bits 57:0) — Reserved writes-preserve-values fields; preserve these bits when writing other fields and do not rely on read values.

What This Field Controls

  • - Reserved writes-preserve-values fields; preserve these bits when writing other fields and do not rely on read values.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mcyclecfg is a 64-bit machine counter-configuration CSR. Smcntrpmf uses it to control whether mcycle continues counting in different privilege modes; on RV32, mcyclecfgh accesses the upper 32 bits.

The official Smcntrpmf table defines mcyclecfg as a 64-bit register with MINH/SINH/UINH/VSINH/VUINH in bits 62..58.
When all xINH bits are zero, counting is enabled in all modes; bits for unimplemented associated privilege modes are read-only zero.
This CSR filters counting itself; it does not decide whether lower-privilege software may read the counter.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISARISC-V Smcntrpmf Extension

What To Check First When Reading This CSR

  • - mcyclecfg belongs to the Smcntrpmf extension; confirm implementation support before use, because an unimplemented CSR access may raise an illegal-instruction exception.
  • - Read the xINH bits to determine whether mcycle is filtered in each privilege mode; bits for unimplemented associated privilege modes are read-only zero by specification.
  • - On RV32, mcyclecfgh accesses bits 63:32 of mcyclecfg.

Risk Checks Before Writing

  • - Modify only the target xINH bits and preserve WPRI bits.
  • - mcyclecfg controls counting filters, not lower-privilege read permission; do not use it as a substitute for mcounteren/scounteren or relevant delegation mechanisms.
  • - If the system uses the Hypervisor extension, confirm that VSINH/VUINH match the guest-profiling policy.

Put It Back Into A Real Flow

1

Confirm that the hart implements Smcntrpmf, then read the current filtering state from mcyclecfg.

2

Set MINH/SINH/UINH/VSINH/VUINH according to the profiling target, filtering only the privilege modes that should not be counted.

3

Validate the counting behavior with mcycle readings and the lower-privilege access-control CSRs.

FAQ

Can mcyclecfg be accessed from any privilege level?

No. The official CSR table lists mcyclecfg as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

How is mcyclecfg different from mcountinhibit?

mcountinhibit inhibits incrementing for a counter as a whole; mcyclecfg filters mcycle counting by privilege mode. Neither is the same as lower-privilege access authorization.