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CSR Bit Fields

RISC-V mcyclecfgh CSR Register

Address 0x721Privilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs

mcyclecfgh at 0x721 is the RV32 machine high-half CSR for bits 63:32 of mcyclecfg.

Related Search Terms
mcyclecfgh CSRmcyclecfgh 0x721mcyclecfg high halfRV32 high halfSmcntrpmfxINH bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:32WPRI25:0WPRI
Field Map

Understand mcyclecfgh By Bit Fields

7 key fields
31

ZERO

RO 0

Corresponds to mcyclecfg[63], defined by Smcntrpmf as read-only zero at the OF position.

ZERO (bit 31) — Corresponds to mcyclecfg[63], defined by Smcntrpmf as read-only zero at the OF position.

What This Field Controls

  • - Corresponds to mcyclecfg[63], defined by Smcntrpmf as read-only zero at the OF position.

Common Values

mcyclecfgh.ZERO
0Read-only zero

This bit corresponds to the Sscofpmf OF position, but Smcntrpmf defines it as read-only 0 for cycle/instret configuration; software must not write 1 or depend on a meaning for 1.

30

MINH

RW

Corresponds to mcyclecfg[62]; when set, inhibits M-mode counting.

MINH (bit 30) — Corresponds to mcyclecfg[62]; when set, inhibits M-mode counting.

What This Field Controls

  • - Corresponds to mcyclecfg[62]; when set, inhibits M-mode counting.

Common Values

MINH mode-filter bit
0Counting allowed

cycle counting in M-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in M-mode is inhibited.

29

SINH

RW

Corresponds to mcyclecfg[61]; when set, inhibits S/HS-mode counting.

SINH (bit 29) — Corresponds to mcyclecfg[61]; when set, inhibits S/HS-mode counting.

What This Field Controls

  • - Corresponds to mcyclecfg[61]; when set, inhibits S/HS-mode counting.

Common Values

SINH mode-filter bit
0Counting allowed

cycle counting in S/HS-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in S/HS-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

28

UINH

RW

Corresponds to mcyclecfg[60]; when set, inhibits U-mode counting.

UINH (bit 28) — Corresponds to mcyclecfg[60]; when set, inhibits U-mode counting.

What This Field Controls

  • - Corresponds to mcyclecfg[60]; when set, inhibits U-mode counting.

Common Values

UINH mode-filter bit
0Counting allowed

cycle counting in U-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in U-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

27

VSINH

RW

Corresponds to mcyclecfg[59]; when set, inhibits VS-mode counting.

VSINH (bit 27) — Corresponds to mcyclecfg[59]; when set, inhibits VS-mode counting.

What This Field Controls

  • - Corresponds to mcyclecfg[59]; when set, inhibits VS-mode counting.

Common Values

VSINH mode-filter bit
0Counting allowed

cycle counting in VS-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in VS-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

26

VUINH

RW

Corresponds to mcyclecfg[58]; when set, inhibits VU-mode counting.

VUINH (bit 26) — Corresponds to mcyclecfg[58]; when set, inhibits VU-mode counting.

What This Field Controls

  • - Corresponds to mcyclecfg[58]; when set, inhibits VU-mode counting.

Common Values

VUINH mode-filter bit
0Counting allowed

cycle counting in VU-mode is not inhibited by this bit; other counter configuration and implementation support still apply.

1Counting inhibited

cycle counting in VU-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

25:0

WPRI

WPRI

Corresponds to reserved writes-preserve-values fields in the underlying 64-bit register.

WPRI (bits 25:0) — Corresponds to reserved writes-preserve-values fields in the underlying 64-bit register.

What This Field Controls

  • - Corresponds to reserved writes-preserve-values fields in the underlying 64-bit register.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mcyclecfgh is the RV32 high-half CSR for bits 63:32 of mcyclecfg, mainly carrying Smcntrpmf mode-filtering control bits.

Smcntrpmf defines mcyclecfg as a 64-bit register, with mcyclecfgh accessing the upper 32 bits on RV32.
mcyclecfgh[30:26] correspond to MINH/SINH/UINH/VSINH/VUINH in mcyclecfg[62:58].
WPRI bits must be preserved on writes.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISARISC-V Smcntrpmf Extension

What To Check First When Reading This CSR

  • - mcyclecfgh is an RV32-only high-half CSR; it should not be used as a separate CSR when XLEN=64.
  • - Reading it is equivalent to reading bits 63:32 of mcyclecfg.
  • - xINH bits for unimplemented associated privilege modes are read-only zero.

Risk Checks Before Writing

  • - Write only the high-half xINH bits that must change and preserve WPRI bits.
  • - Writing mcyclecfgh changes the upper 32 bits of mcyclecfg; avoid conflicting with full mcyclecfg write paths.

Put It Back Into A Real Flow

1

On RV32, read mcyclecfgh to observe the high-half configuration of mcyclecfg.

2

Adjust the required xINH bits.

3

Validate the filtering policy with mcycle count results.

FAQ

Can mcyclecfgh be accessed from any privilege level?

No. The official CSR table lists mcyclecfgh as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

Does mcyclecfgh exist on RV64?

Not as a separate high-half CSR. RV64 accesses the full 64-bit configuration directly through mcyclecfg.