RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V mcountinhibit CSR Register

Address 0x320Privilege MachineAccess RW / 32Machine counters and performance-monitoring CSRs

mcountinhibit controls whether machine counters such as cycle and instret are allowed to increment.

Related Search Terms
mcountinhibit CSRmcountinhibit 0x320counter inhibit CSRmcountinhibit CY IRmcountinhibit HPMnmachine counter control
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:32HPMn31:3WARLIR2WARLreserved1reservedCY0WARL
Field Map

Understand mcountinhibit By Bit Fields

4 key fields
0

CY

WARL

Inhibits mcycle counting; meaningful only for implemented counters.

CY (bit 0) — Inhibits mcycle counting; meaningful only for implemented counters.

What This Field Controls

  • - Inhibits mcycle counting; meaningful only for implemented counters.

Common Values

0Increment enabled

mcycle is not inhibited by this bit.

1Increment inhibited

mcycle incrementing is inhibited; this is meaningful only for implemented counters.

1

reserved

reserved

Reserved; there is no machine-level time counter.

reserved (bit 1) — Reserved; there is no machine-level time counter.

What This Field Controls

  • - Reserved; there is no machine-level time counter.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

2

IR

WARL

Inhibits minstret counting; meaningful only for implemented counters.

IR (bit 2) — Inhibits minstret counting; meaningful only for implemented counters.

What This Field Controls

  • - Inhibits minstret counting; meaningful only for implemented counters.

Common Values

0Increment enabled

minstret is not inhibited by this bit.

1Increment inhibited

minstret incrementing is inhibited; this is meaningful only for implemented counters.

31:3

HPMn

WARL

Inhibits corresponding mhpmcounter3..31 counting; meaningful only for implemented HPM counters.

HPMn (bits 31:3) — Inhibits corresponding mhpmcounter3..31 counting; meaningful only for implemented HPM counters.

What This Field Controls

  • - Inhibits corresponding mhpmcounter3..31 counting; meaningful only for implemented HPM counters.

Common Values

0Increment enabled

The corresponding mhpmcounter3-31 counter is not inhibited by this bit.

1Increment inhibited

Incrementing of the corresponding mhpmcounter3-31 counter is inhibited; this is meaningful only for implemented counters.

Official Basis & Search Notes

mcountinhibit is a RW CSR in machine counters and performance-monitoring csrs at 0x320. Check privilege and implemented extensions before interpreting its bit fields.

mcountinhibit address, lowest access privilege, and access class are checked against the official CSR table: 0x320, Machine, RW.
It is a 32-bit WARL CSR whose CY, IR, and HPMn bits inhibit incrementing of corresponding implemented counters.
Bit 1 is reserved; do not treat mcountinhibit as an XLEN-wide ordinary integer field.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mcountinhibit; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x320 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mcountinhibit to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mcountinhibit be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mcountinhibit as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mcountinhibit?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.