mcountinhibit controls whether machine counters such as cycle and instret are allowed to increment.
Inhibits mcycle counting; meaningful only for implemented counters.
CY (bit 0) — Inhibits mcycle counting; meaningful only for implemented counters.
mcycle is not inhibited by this bit.
mcycle incrementing is inhibited; this is meaningful only for implemented counters.
Reserved; there is no machine-level time counter.
reserved (bit 1) — Reserved; there is no machine-level time counter.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Inhibits minstret counting; meaningful only for implemented counters.
IR (bit 2) — Inhibits minstret counting; meaningful only for implemented counters.
minstret is not inhibited by this bit.
minstret incrementing is inhibited; this is meaningful only for implemented counters.
Inhibits corresponding mhpmcounter3..31 counting; meaningful only for implemented HPM counters.
HPMn (bits 31:3) — Inhibits corresponding mhpmcounter3..31 counting; meaningful only for implemented HPM counters.
The corresponding mhpmcounter3-31 counter is not inhibited by this bit.
Incrementing of the corresponding mhpmcounter3-31 counter is inhibited; this is meaningful only for implemented counters.
mcountinhibit is a 32-bit register; in the RV64 CSR view, bits 63:32 are outside that 32-bit counter-inhibit bitmap and read as zero.
Reserved/RO0 (RV64) (bits 63:32) — mcountinhibit is a 32-bit register; in the RV64 CSR view, bits 63:32 are outside that 32-bit counter-inhibit bitmap and read as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
mcountinhibit is a 32-bit machine WARL CSR at 0x320. It inhibits incrementing per counter without changing lower-privilege access control.
During initialization or the relevant privileged flow, software reads mcountinhibit to observe the current state.
Modify only the target fields while preserving all other bits.
Read the counter or mcountinhibit after the write to verify that the target counter stops or resumes incrementing as intended.
Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; mcountinhibit is a Machine CSR. If it is not implemented, the specification requires hardware to behave as if it were zero.
Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.