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CSR Bit Fields

RISC-V mhpmevent3 CSR Register

Address 0x323Privilege MachineAccess RW / 64Machine counters and performance-monitoring CSRs

mhpmevent3 at 0x323 is the machine HPM event-selector CSR for mhpmcounter3; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

Related Search Terms
mhpmevent3 CSRmhpmevent3 0x323mhpmcounter3 eventHPM event selectorSscofpmfOF bitxINH bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
OF63RWEVENT55:0WARL
Field Map

Understand mhpmevent3 By Bit Fields

8 key fields
63

OF

RW

Sscofpmf overflow status and interrupt-disable bit; set when mhpmcounter3 overflows.

OF (bit 63) — Sscofpmf overflow status and interrupt-disable bit; set when mhpmcounter3 overflows.

What This Field Controls

  • - Sscofpmf overflow status and interrupt-disable bit; set when mhpmcounter3 overflows.

Common Values

Sscofpmf OF bit
0No overflow recorded

The OF bit for mhpmcounter3 is clear; this bit itself does not disable generation of a later count-overflow interrupt request.

1Overflow recorded

mhpmcounter3 has overflowed and set the sticky OF bit; it remains set until cleared by software and disables new count-overflow interrupt requests for this counter.

62

MINH

RW

When set, inhibits event counting in M-mode.

MINH (bit 62) — When set, inhibits event counting in M-mode.

What This Field Controls

  • - When set, inhibits event counting in M-mode.

Common Values

MINH mode-filter bit
0Counting allowed

mhpmcounter3 event counting in M-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter3 event counting in M-mode is inhibited.

61

SINH

RW

When set, inhibits event counting in S/HS-mode; if the associated privilege mode is not implemented, this bit is read-only zero.

SINH (bit 61) — When set, inhibits event counting in S/HS-mode; if the associated privilege mode is not implemented, this bit is read-only zero.

What This Field Controls

  • - When set, inhibits event counting in S/HS-mode; if the associated privilege mode is not implemented, this bit is read-only zero.

Common Values

SINH mode-filter bit
0Counting allowed

mhpmcounter3 event counting in S/HS-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter3 event counting in S/HS-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

60

UINH

RW

When set, inhibits event counting in U-mode; if U-mode is not implemented, this bit is read-only zero.

UINH (bit 60) — When set, inhibits event counting in U-mode; if U-mode is not implemented, this bit is read-only zero.

What This Field Controls

  • - When set, inhibits event counting in U-mode; if U-mode is not implemented, this bit is read-only zero.

Common Values

UINH mode-filter bit
0Counting allowed

mhpmcounter3 event counting in U-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter3 event counting in U-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

59

VSINH

RW

When set, inhibits event counting in VS-mode; if Hypervisor/VS mode is not implemented, this bit is read-only zero.

VSINH (bit 59) — When set, inhibits event counting in VS-mode; if Hypervisor/VS mode is not implemented, this bit is read-only zero.

What This Field Controls

  • - When set, inhibits event counting in VS-mode; if Hypervisor/VS mode is not implemented, this bit is read-only zero.

Common Values

VSINH mode-filter bit
0Counting allowed

mhpmcounter3 event counting in VS-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter3 event counting in VS-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

58

VUINH

RW

When set, inhibits event counting in VU-mode; if VU-mode is not implemented, this bit is read-only zero.

VUINH (bit 58) — When set, inhibits event counting in VU-mode; if VU-mode is not implemented, this bit is read-only zero.

What This Field Controls

  • - When set, inhibits event counting in VU-mode; if VU-mode is not implemented, this bit is read-only zero.

Common Values

VUINH mode-filter bit
0Counting allowed

mhpmcounter3 event counting in VU-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter3 event counting in VU-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

57:56

WPRI

WPRI

Sscofpmf reserved writes-preserve-values fields.

WPRI (bits 57:56) — Sscofpmf reserved writes-preserve-values fields.

What This Field Controls

  • - Sscofpmf reserved writes-preserve-values fields.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

55:0

EVENT

WARL

Platform-defined event selector for mhpmcounter3; event 0 means no event is counted.

EVENT (bits 55:0) — Platform-defined event selector for mhpmcounter3; event 0 means no event is counted.

What This Field Controls

  • - Platform-defined event selector for mhpmcounter3; event 0 means no event is counted.

Common Values

mhpmevent EVENT selector
0No event

The official specification defines EVENT=0 to mean mhpmcounter3 counts no event; other EVENT encodings are platform-defined and are not enumerated on the generic page.

Official Basis & Search Notes

mhpmevent3 decides which platform-defined performance event mhpmcounter3 counts. If Sscofpmf is implemented, upper bits also contain the OF overflow status/interrupt-disable bit and MINH/SINH/UINH/VSINH/VUINH mode-filtering bits.

The official Machine HPM mechanism uses mhpmevent3 as the event-selector CSR for mhpmcounter3.
Event selector encodings are platform-defined; a generic page must not invent concrete platform event numbers.
Sscofpmf standardizes the OF and xINH upper bits and exposes OF shadows through scountovf.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISARISC-V Sscofpmf Extension

What To Check First When Reading This CSR

  • - Confirm that the current hart implements mhpmevent3 and the associated HPM counter; unimplemented counters may read as zero.
  • - Event encodings are platform-defined, so do not infer event meaning from the mhpmevent3 name alone.
  • - When Sscofpmf is implemented, the OF bit is also reflected read-only in the corresponding bit of scountovf.

Risk Checks Before Writing

  • - Check target platform event encodings before writing an event selector and preserve WPRI bits.
  • - Changing OF/xINH bits affects overflow interrupt behavior or privilege-mode filtering; do not overwrite mhpmevent3 as an ordinary integer.
  • - Lower-privilege reads of mhpmcounter3 or hpmcounter3 are still controlled by counteren/delegation mechanisms.

Put It Back Into A Real Flow

1

Confirm that the target platform defines the event encoding to use with mhpmevent3.

2

Configure the EVENT field and set OF or xINH bits as needed.

3

Read mhpmcounter3 or the corresponding lower-privilege shadow counter to validate event counting and overflow behavior.

FAQ

Can mhpmevent3 be accessed from any privilege level?

No. The official CSR table lists mhpmevent3 as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

Does mhpmevent3 directly define what each event number means?

No. RISC-V defines the HPM event-selector mechanism, but concrete event encodings are platform-defined; this page only states the standardized OF/xINH fields and the relationship with mhpmcounter3.