RISC-V mhpmcounter3 CSR Register

Address 0xB03Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter3 at 0xB03 is machine hardware performance-monitor counter 3, with up to 64 bits of precision for the event selected by mhpmevent3.

Related Search Terms

mhpmcounter3 CSR mhpmcounter3 0xB03 HPM counter 3 mhpmevent3 event machine performance counter up to 64-bit precision

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter3 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent3; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent3 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent3; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent3 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent3; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent3 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter3 is machine HPM counter 3. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent3.

The official machine HPM mechanism defines mhpmcounter3 as a WARL counter with up to 64 bits of precision.

mhpmevent3 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter3h accesses bits 63:32; a legal implementation may make both mhpmcounter3 and mhpmevent3 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter3 is selected by mhpmevent3; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter3 view are controlled by mcounteren.HPM3; U-mode is additionally controlled by scounteren.HPM3.
- On RV32, mhpmcounter3h accesses bits 63:32 of mhpmcounter3.

Risk Checks Before Writing

- Writing mhpmcounter3 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM3 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent3 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent3 to select the platform-defined event to count.

Set mcountinhibit.HPM3 when needed to stop mhpmcounter3 from incrementing.

Read mhpmcounter3; on RV32, also read mhpmcounter3h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter3 be accessed from any privilege level?

No. The CSR table lists mhpmcounter3 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter3 view: S/U-mode reads are controlled by mcounteren.HPM3, and U-mode reads are additionally controlled by scounteren.HPM3. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter3 related to hpmcounter3?

mhpmcounter3 is the machine read/write counter; hpmcounter3 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM3, and U-mode reads are additionally controlled by scounteren.HPM3.