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CSR Bit Fields

RISC-V scountovf CSR Register

Address 0xDA0Privilege SupervisorAccess RO / 32Supervisor counters and overflow CSRs

scountovf (0xDA0) is the Sscofpmf 32-bit read-only CSR holding shadow copies of the OF overflow-status bits in mhpmevent3 through mhpmevent31.

Related Search Terms
scountovf CSRscountovf 0xDA0counter overflow CSRsupervisor counter overflowLCOFI overflow stateRISC-V scountovf
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
RO063:32RO 0OF_SHADOW31:3RORO02:0RO 0
Field Map

Understand scountovf By Bit Fields

3 key fields
31:3

OF_SHADOW

RO

Bit X is the read-only shadow of mhpmeventX.OF (X=3..31). It is always readable in M-mode; S/HS-mode requires mcounteren[X]=1 and otherwise reads zero. In VS-mode, a read raises a virtual-instruction exception when Smcdeleg/Ssccfg, Sscofpmf, and H are implemented with menvcfg.CDE=1; otherwise both mcounteren[X] and hcounteren[X] must be 1, and the bit otherwise reads zero.

OF_SHADOW (bits 31:3) — Bit X is the read-only shadow of mhpmeventX.OF (X=3..31). It is always readable in M-mode; S/HS-mode requires mcounteren[X]=1 and otherwise reads zero. In VS-mode, a read raises a virtual-instruction exception when Smcdeleg/Ssccfg, Sscofpmf, and H are implemented with menvcfg.CDE=1; otherwise both mcounteren[X] and hcounteren[X] must be 1, and the bit otherwise reads zero.

What This Field Controls

  • - Bit X is the read-only shadow of mhpmeventX.OF (X=3..31). It is always readable in M-mode; S/HS-mode requires mcounteren[X]=1 and otherwise reads zero. In VS-mode, a read raises a virtual-instruction exception when Smcdeleg/Ssccfg, Sscofpmf, and H are implemented with menvcfg.CDE=1; otherwise both mcounteren[X] and hcounteren[X] must be 1, and the bit otherwise reads zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
2:0

RO0

RO 0

There are no OF shadows for mhpmevent0, mhpmevent1, or mhpmevent2; scountovf maps only mhpmevent3 through mhpmevent31.

RO0 (bits 2:0) — There are no OF shadows for mhpmevent0, mhpmevent1, or mhpmevent2; scountovf maps only mhpmevent3 through mhpmevent31.

What This Field Controls

  • - There are no OF shadows for mhpmevent0, mhpmevent1, or mhpmevent2; scountovf maps only mhpmevent3 through mhpmevent31.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
63:32

RO0

RO 0

scountovf is a 32-bit register; on RV64, bits 63:32 are outside that 32-bit OF shadow register and read as zero.

RO0 (bits 63:32) — scountovf is a 32-bit register; on RV64, bits 63:32 are outside that 32-bit OF shadow register and read as zero.

What This Field Controls

  • - scountovf is a 32-bit register; on RV64, bits 63:32 are outside that 32-bit OF shadow register and read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

scountovf is Sscofpmf's 32-bit read-only shadow register: bit X reports mhpmeventX.OF for X=3..31, although counteren gating in the current mode can make a bit read zero; a particular Smcdeleg/Ssccfg, H, and CDE combination makes VS/VU reads raise a virtual-instruction exception.

The official CSR table lists scountovf as 0xDA0 SRO; Sscofpmf defines it as a 32-bit register.
Bit X is the shadow of mhpmeventX.OF for X=3..31; bits 2:0 are read-only zero.
S/HS reads require mcounteren[X]=1. When Smcdeleg/Ssccfg, Sscofpmf, and H are implemented with menvcfg.CDE=1, VS/VU reads raise a virtual-instruction exception; otherwise VS reads require both mcounteren[X] and hcounteren[X] to be 1, and the bit otherwise reads zero.
RISC-V Privileged Architecture ManualRISC-V Privileged Architecture Manual - Sscofpmf

What To Check First When Reading This CSR

  • - scountovf is defined by Sscofpmf as a 32-bit read-only register, not an XLEN-wide general state value.
  • - Bit X reflects mhpmeventX.OF for X=3..31; bits 2:0 are read-only zero.
  • - In S/HS-mode, a bit with mcounteren[X]=0 reads as zero. In VS-mode, a read raises a virtual-instruction exception when Smcdeleg/Ssccfg, Sscofpmf, and H are implemented with menvcfg.CDE=1; otherwise both mcounteren[X] and hcounteren[X] are required.

Risk Checks Before Writing

  • - scountovf is read-only; do not use it to clear OF bits. Handle them through the corresponding writable event selector under the mhpmeventX.OF rules.

Put It Back Into A Real Flow

1

Confirm Sscofpmf and configure the required counteren access for the target HPM bits in the current mode; in VS-mode first check whether Smcdeleg/Ssccfg, H, and menvcfg.CDE=1 make a read raise a virtual-instruction exception.

2

Read bits 31:3 and use bit X as mhpmeventX.OF to identify overflowed counters.

3

Handle a local counter-overflow interrupt with the LCOFIP/LCOFIE and OF software-clear rules; do not write scountovf.

FAQ

Why does a scountovf bit read as zero?

Besides an OF bit being zero, S/HS-mode may have mcounteren[X]=0. In VS-mode, a read raises a virtual-instruction exception when Smcdeleg/Ssccfg, Sscofpmf, and H are implemented with menvcfg.CDE=1; otherwise both mcounteren[X] and hcounteren[X] must be 1, and the bit reads zero when either gate is not met.

What is easiest to miss when using scountovf?

It is a read-only shadow and does not clear OF. Clear OF through the corresponding writable event selector under the mhpmeventX.OF rules, together with LCOFIP/LCOFIE interrupt handling.