RISC-V mhpmcounter11 CSR Register

Address 0xB0BPrivilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter11 at 0xB0B is machine hardware performance-monitor counter 11, with up to 64 bits of precision for the event selected by mhpmevent11.

Related Search Terms

mhpmcounter11 CSR mhpmcounter11 0xB0B HPM counter 11 mhpmevent11 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter11 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent11; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent11 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent11; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent11 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent11; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent11 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter11 is machine HPM counter 11. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent11.

The official machine HPM mechanism defines mhpmcounter11 as a WARL counter with up to 64 bits of precision.

mhpmevent11 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter11h accesses bits 63:32; a legal implementation may make both mhpmcounter11 and mhpmevent11 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter11 is selected by mhpmevent11; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter11 view are controlled by mcounteren.HPM11; U-mode is additionally controlled by scounteren.HPM11.
- On RV32, mhpmcounter11h accesses bits 63:32 of mhpmcounter11.

Risk Checks Before Writing

- Writing mhpmcounter11 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM11 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent11 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent11 to select the platform-defined event to count.

Set mcountinhibit.HPM11 when needed to stop mhpmcounter11 from incrementing.

Read mhpmcounter11; on RV32, also read mhpmcounter11h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter11 be accessed from any privilege level?

No. The CSR table lists mhpmcounter11 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter11 view: S/U-mode reads are controlled by mcounteren.HPM11, and U-mode reads are additionally controlled by scounteren.HPM11. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter11 related to hpmcounter11?

mhpmcounter11 is the machine read/write counter; hpmcounter11 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM11, and U-mode reads are additionally controlled by scounteren.HPM11.