RISC-V mhpmcounter12 CSR Register

Address 0xB0CPrivilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter12 at 0xB0C is machine hardware performance-monitor counter 12, with up to 64 bits of precision for the event selected by mhpmevent12.

Related Search Terms

mhpmcounter12 CSR mhpmcounter12 0xB0C HPM counter 12 mhpmevent12 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter12 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent12; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent12 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent12; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent12 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent12; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent12 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter12 is machine HPM counter 12. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent12.

The official machine HPM mechanism defines mhpmcounter12 as a WARL counter with up to 64 bits of precision.

mhpmevent12 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter12h accesses bits 63:32; a legal implementation may make both mhpmcounter12 and mhpmevent12 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter12 is selected by mhpmevent12; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter12 view are controlled by mcounteren.HPM12; U-mode is additionally controlled by scounteren.HPM12.
- On RV32, mhpmcounter12h accesses bits 63:32 of mhpmcounter12.

Risk Checks Before Writing

- Writing mhpmcounter12 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM12 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent12 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent12 to select the platform-defined event to count.

Set mcountinhibit.HPM12 when needed to stop mhpmcounter12 from incrementing.

Read mhpmcounter12; on RV32, also read mhpmcounter12h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter12 be accessed from any privilege level?

No. The CSR table lists mhpmcounter12 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter12 view: S/U-mode reads are controlled by mcounteren.HPM12, and U-mode reads are additionally controlled by scounteren.HPM12. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter12 related to hpmcounter12?

mhpmcounter12 is the machine read/write counter; hpmcounter12 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM12, and U-mode reads are additionally controlled by scounteren.HPM12.