RISC-V mhpmcounter14 CSR Register

Address 0xB0EPrivilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter14 at 0xB0E is machine hardware performance-monitor counter 14, with up to 64 bits of precision for the event selected by mhpmevent14.

Related Search Terms

mhpmcounter14 CSR mhpmcounter14 0xB0E HPM counter 14 mhpmevent14 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter14 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent14; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent14 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent14; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent14 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent14; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent14 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter14 is machine HPM counter 14. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent14.

The official machine HPM mechanism defines mhpmcounter14 as a WARL counter with up to 64 bits of precision.

mhpmevent14 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter14h accesses bits 63:32; a legal implementation may make both mhpmcounter14 and mhpmevent14 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter14 is selected by mhpmevent14; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter14 view are controlled by mcounteren.HPM14; U-mode is additionally controlled by scounteren.HPM14.
- On RV32, mhpmcounter14h accesses bits 63:32 of mhpmcounter14.

Risk Checks Before Writing

- Writing mhpmcounter14 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM14 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent14 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent14 to select the platform-defined event to count.

Set mcountinhibit.HPM14 when needed to stop mhpmcounter14 from incrementing.

Read mhpmcounter14; on RV32, also read mhpmcounter14h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter14 be accessed from any privilege level?

No. The CSR table lists mhpmcounter14 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter14 view: S/U-mode reads are controlled by mcounteren.HPM14, and U-mode reads are additionally controlled by scounteren.HPM14. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter14 related to hpmcounter14?

mhpmcounter14 is the machine read/write counter; hpmcounter14 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM14, and U-mode reads are additionally controlled by scounteren.HPM14.