Can mhpmcounter16h be accessed from any privilege level?
No. The official CSR table lists mhpmcounter16h as an RV32-only Machine read/write CSR.
CSR Bit Fields
RISC-V mhpmcounter16h CSR Register
Address 0xB90Privilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs
mhpmcounter16h at 0xB90 is the RV32 machine high-half CSR for bits 63:32 of mhpmcounter16.
Bit Overview
Hover for details · Click to jumpbit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map
Understand mhpmcounter16h By Bit Fields
0 key fields
Official Basis & Search Notes
mhpmcounter16h is the RV32 high-half access CSR for bits 63:32 of mhpmcounter16; its event meaning is still determined by mhpmevent16.
mhpmcounter16 is a WARL register with up to 64 bits of precision; RV32 accesses it through low/high halves mhpmcounter16/mhpmcounter16h.
On RV32, the high-half CSR accesses bits 63:32 and the low-half CSR accesses bits 31:0.
mhpmcounter16h does not select the event; event selection is in mhpmevent16.
What To Check First When Reading This CSR
- - mhpmcounter16h exists only on RV32.
- - mhpmcounter16 is a WARL register with up to 64 bits of precision; event meanings are platform-defined.
- - mcountinhibit.HPM16 controls only whether mhpmcounter16 increments, not its accessibility.
Risk Checks Before Writing
- - On RV32, writing mhpmcounter16h changes only bits 63:32 of mhpmcounter16.
- - A legal implementation may make both mhpmcounter16 and its mhpmevent16 selector read-only zero.
Put It Back Into A Real Flow
1
On RV32, access mhpmcounter16h and mhpmcounter16 separately.
2
The high and low halves correspond to bits 63:32 and 31:0 of one WARL counter.
3
Use mhpmevent16 to determine the platform-selected event for the counter.
FAQ
Is mhpmcounter16h a separate counter?
No. It is only the RV32 access CSR for the upper 32 bits of mhpmcounter16.