RISC-V mhpmcounter16 CSR Register

Address 0xB10Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter16 at 0xB10 is machine hardware performance-monitor counter 16, with up to 64 bits of precision for the event selected by mhpmevent16.

Related Search Terms

mhpmcounter16 CSR mhpmcounter16 0xB10 HPM counter 16 mhpmevent16 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter16 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent16; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent16 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent16; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent16 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent16; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent16 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter16 is machine HPM counter 16. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent16.

The official machine HPM mechanism defines mhpmcounter16 as a WARL counter with up to 64 bits of precision.

mhpmevent16 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter16h accesses bits 63:32; a legal implementation may make both mhpmcounter16 and mhpmevent16 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter16 is selected by mhpmevent16; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter16 view are controlled by mcounteren.HPM16; U-mode is additionally controlled by scounteren.HPM16.
- On RV32, mhpmcounter16h accesses bits 63:32 of mhpmcounter16.

Risk Checks Before Writing

- Writing mhpmcounter16 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM16 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent16 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent16 to select the platform-defined event to count.

Set mcountinhibit.HPM16 when needed to stop mhpmcounter16 from incrementing.

Read mhpmcounter16; on RV32, also read mhpmcounter16h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter16 be accessed from any privilege level?

No. The CSR table lists mhpmcounter16 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter16 view: S/U-mode reads are controlled by mcounteren.HPM16, and U-mode reads are additionally controlled by scounteren.HPM16. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter16 related to hpmcounter16?

mhpmcounter16 is the machine read/write counter; hpmcounter16 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM16, and U-mode reads are additionally controlled by scounteren.HPM16.