RISC-V mhpmcounter17 CSR Register

Address 0xB11Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter17 at 0xB11 is machine hardware performance-monitor counter 17, with up to 64 bits of precision for the event selected by mhpmevent17.

Related Search Terms

mhpmcounter17 CSR mhpmcounter17 0xB11 HPM counter 17 mhpmevent17 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter17 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent17; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent17 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent17; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent17 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent17; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent17 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter17 is machine HPM counter 17. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent17.

The official machine HPM mechanism defines mhpmcounter17 as a WARL counter with up to 64 bits of precision.

mhpmevent17 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter17h accesses bits 63:32; a legal implementation may make both mhpmcounter17 and mhpmevent17 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter17 is selected by mhpmevent17; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter17 view are controlled by mcounteren.HPM17; U-mode is additionally controlled by scounteren.HPM17.
- On RV32, mhpmcounter17h accesses bits 63:32 of mhpmcounter17.

Risk Checks Before Writing

- Writing mhpmcounter17 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM17 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent17 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent17 to select the platform-defined event to count.

Set mcountinhibit.HPM17 when needed to stop mhpmcounter17 from incrementing.

Read mhpmcounter17; on RV32, also read mhpmcounter17h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter17 be accessed from any privilege level?

No. The CSR table lists mhpmcounter17 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter17 view: S/U-mode reads are controlled by mcounteren.HPM17, and U-mode reads are additionally controlled by scounteren.HPM17. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter17 related to hpmcounter17?

mhpmcounter17 is the machine read/write counter; hpmcounter17 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM17, and U-mode reads are additionally controlled by scounteren.HPM17.