Can mhpmcounter19h be accessed from any privilege level?
No. The official CSR table lists mhpmcounter19h as an RV32-only Machine read/write CSR.
CSR Bit Fields
RISC-V mhpmcounter19h CSR Register
Address 0xB93Privilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs
mhpmcounter19h at 0xB93 is the RV32 machine high-half CSR for bits 63:32 of mhpmcounter19.
Bit Overview
Hover for details · Click to jumpbit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map
Understand mhpmcounter19h By Bit Fields
0 key fields
Official Basis & Search Notes
mhpmcounter19h is the RV32 high-half access CSR for bits 63:32 of mhpmcounter19; its event meaning is still determined by mhpmevent19.
mhpmcounter19 is a WARL register with up to 64 bits of precision; RV32 accesses it through low/high halves mhpmcounter19/mhpmcounter19h.
On RV32, the high-half CSR accesses bits 63:32 and the low-half CSR accesses bits 31:0.
mhpmcounter19h does not select the event; event selection is in mhpmevent19.
What To Check First When Reading This CSR
- - mhpmcounter19h exists only on RV32.
- - mhpmcounter19 is a WARL register with up to 64 bits of precision; event meanings are platform-defined.
- - mcountinhibit.HPM19 controls only whether mhpmcounter19 increments, not its accessibility.
Risk Checks Before Writing
- - On RV32, writing mhpmcounter19h changes only bits 63:32 of mhpmcounter19.
- - A legal implementation may make both mhpmcounter19 and its mhpmevent19 selector read-only zero.
Put It Back Into A Real Flow
1
On RV32, access mhpmcounter19h and mhpmcounter19 separately.
2
The high and low halves correspond to bits 63:32 and 31:0 of one WARL counter.
3
Use mhpmevent19 to determine the platform-selected event for the counter.
FAQ
Is mhpmcounter19h a separate counter?
No. It is only the RV32 access CSR for the upper 32 bits of mhpmcounter19.