RISC-V mhpmcounter19 CSR Register

Address 0xB13Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter19 at 0xB13 is machine hardware performance-monitor counter 19, with up to 64 bits of precision for the event selected by mhpmevent19.

Related Search Terms

mhpmcounter19 CSR mhpmcounter19 0xB13 HPM counter 19 mhpmevent19 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter19 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent19; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent19 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent19; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent19 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent19; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent19 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter19 is machine HPM counter 19. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent19.

The official machine HPM mechanism defines mhpmcounter19 as a WARL counter with up to 64 bits of precision.

mhpmevent19 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter19h accesses bits 63:32; a legal implementation may make both mhpmcounter19 and mhpmevent19 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter19 is selected by mhpmevent19; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter19 view are controlled by mcounteren.HPM19; U-mode is additionally controlled by scounteren.HPM19.
- On RV32, mhpmcounter19h accesses bits 63:32 of mhpmcounter19.

Risk Checks Before Writing

- Writing mhpmcounter19 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM19 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent19 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent19 to select the platform-defined event to count.

Set mcountinhibit.HPM19 when needed to stop mhpmcounter19 from incrementing.

Read mhpmcounter19; on RV32, also read mhpmcounter19h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter19 be accessed from any privilege level?

No. The CSR table lists mhpmcounter19 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter19 view: S/U-mode reads are controlled by mcounteren.HPM19, and U-mode reads are additionally controlled by scounteren.HPM19. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter19 related to hpmcounter19?

mhpmcounter19 is the machine read/write counter; hpmcounter19 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM19, and U-mode reads are additionally controlled by scounteren.HPM19.