Can mhpmcounter20h be accessed from any privilege level?
No. The official CSR table lists mhpmcounter20h as an RV32-only Machine read/write CSR.
CSR Bit Fields
RISC-V mhpmcounter20h CSR Register
Address 0xB94Privilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs
mhpmcounter20h at 0xB94 is the RV32 machine high-half CSR for bits 63:32 of mhpmcounter20.
Bit Overview
Hover for details · Click to jumpbit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map
Understand mhpmcounter20h By Bit Fields
0 key fields
Official Basis & Search Notes
mhpmcounter20h is the RV32 high-half access CSR for bits 63:32 of mhpmcounter20; its event meaning is still determined by mhpmevent20.
mhpmcounter20 is a WARL register with up to 64 bits of precision; RV32 accesses it through low/high halves mhpmcounter20/mhpmcounter20h.
On RV32, the high-half CSR accesses bits 63:32 and the low-half CSR accesses bits 31:0.
mhpmcounter20h does not select the event; event selection is in mhpmevent20.
What To Check First When Reading This CSR
- - mhpmcounter20h exists only on RV32.
- - mhpmcounter20 is a WARL register with up to 64 bits of precision; event meanings are platform-defined.
- - mcountinhibit.HPM20 controls only whether mhpmcounter20 increments, not its accessibility.
Risk Checks Before Writing
- - On RV32, writing mhpmcounter20h changes only bits 63:32 of mhpmcounter20.
- - A legal implementation may make both mhpmcounter20 and its mhpmevent20 selector read-only zero.
Put It Back Into A Real Flow
1
On RV32, access mhpmcounter20h and mhpmcounter20 separately.
2
The high and low halves correspond to bits 63:32 and 31:0 of one WARL counter.
3
Use mhpmevent20 to determine the platform-selected event for the counter.
FAQ
Is mhpmcounter20h a separate counter?
No. It is only the RV32 access CSR for the upper 32 bits of mhpmcounter20.