RISC-V mhpmcounter20 CSR Register

Address 0xB14Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter20 at 0xB14 is machine hardware performance-monitor counter 20, with up to 64 bits of precision for the event selected by mhpmevent20.

Related Search Terms

mhpmcounter20 CSR mhpmcounter20 0xB14 HPM counter 20 mhpmevent20 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter20 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent20; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent20 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent20; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent20 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent20; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent20 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter20 is machine HPM counter 20. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent20.

The official machine HPM mechanism defines mhpmcounter20 as a WARL counter with up to 64 bits of precision.

mhpmevent20 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter20h accesses bits 63:32; a legal implementation may make both mhpmcounter20 and mhpmevent20 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter20 is selected by mhpmevent20; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter20 view are controlled by mcounteren.HPM20; U-mode is additionally controlled by scounteren.HPM20.
- On RV32, mhpmcounter20h accesses bits 63:32 of mhpmcounter20.

Risk Checks Before Writing

- Writing mhpmcounter20 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM20 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent20 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent20 to select the platform-defined event to count.

Set mcountinhibit.HPM20 when needed to stop mhpmcounter20 from incrementing.

Read mhpmcounter20; on RV32, also read mhpmcounter20h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter20 be accessed from any privilege level?

No. The CSR table lists mhpmcounter20 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter20 view: S/U-mode reads are controlled by mcounteren.HPM20, and U-mode reads are additionally controlled by scounteren.HPM20. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter20 related to hpmcounter20?

mhpmcounter20 is the machine read/write counter; hpmcounter20 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM20, and U-mode reads are additionally controlled by scounteren.HPM20.