RISC-V mhpmcounter23 CSR Register

Address 0xB17Privilege MachineAccess RW / up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter23 at 0xB17 is machine hardware performance-monitor counter 23, a WARL counter with up to 64 bits of precision for the platform-defined event selected by mhpmevent23.

Related Search Terms

mhpmcounter23 CSR mhpmcounter23 0xB17 HPM counter 23 mhpmevent23 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter23 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the platform-defined event selected by mhpmevent23. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent23 read-only zero.

COUNT (bits 63:0) — Machine HPM count for the platform-defined event selected by mhpmevent23. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent23 read-only zero.

What This Field Controls

- Machine HPM count for the platform-defined event selected by mhpmevent23. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent23 read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter23 is machine HPM counter 23. It does not define event meaning by itself; it counts the platform-defined event currently selected by mhpmevent23 with up to 64 bits of precision.

The official Machine HPM mechanism defines mhpmcounter23 as a WARL counter with up to 64 bits of precision.

mhpmevent23 selects the event; event numbers are platform-defined.

On RV32, mhpmcounter23h provides access to the upper 32 bits.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter23 is determined by mhpmevent23; check the event-selector configuration first.
- S/U-mode reads of the read-only hpmcounter23 shadow are controlled by mcounteren.HPM23; U-mode additionally requires scounteren.HPM23.
- On RV32, mhpmcounter23h accesses bits 63:32 of mhpmcounter23.

Risk Checks Before Writing

- A write to mhpmcounter23 takes effect after the writing instruction has otherwise completed and changes the current count.
- When mcountinhibit.HPM23 is set, the counter does not increment; that bit controls incrementing, not accessibility.

Put It Back Into A Real Flow

Configure mhpmevent23 to select the platform-defined event to count.

Use mcountinhibit.HPM23 when needed to control the counting window.

Read mhpmcounter23 and, on RV32, mhpmcounter23h to obtain the event count with up to 64 bits of precision.

FAQ

Can mhpmcounter23 be accessed from any privilege level?

No. The CSR table lists mhpmcounter23 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter23 view: S/U-mode reads are controlled by mcounteren.HPM23, and U-mode reads are additionally controlled by scounteren.HPM23. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter23 related to hpmcounter23?

mhpmcounter23 is the machine read/write counter; hpmcounter23 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM23, and U-mode reads are additionally controlled by scounteren.HPM23.