RISC-V mhpmcounter24 CSR Register

Address 0xB18Privilege MachineAccess RW / up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter24 at 0xB18 is machine hardware performance-monitor counter 24, a WARL counter with up to 64 bits of precision for the platform-defined event selected by mhpmevent24.

Related Search Terms

mhpmcounter24 CSR mhpmcounter24 0xB18 HPM counter 24 mhpmevent24 event machine performance counter up to 64-bit precision

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter24 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the platform-defined event selected by mhpmevent24. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent24 read-only zero.

COUNT (bits 63:0) — Machine HPM count for the platform-defined event selected by mhpmevent24. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent24 read-only zero.

What This Field Controls

- Machine HPM count for the platform-defined event selected by mhpmevent24. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent24 read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter24 is machine HPM counter 24. It does not define event meaning by itself; it counts the platform-defined event currently selected by mhpmevent24 with up to 64 bits of precision.

The official Machine HPM mechanism defines mhpmcounter24 as a WARL counter with up to 64 bits of precision.

mhpmevent24 selects the event; event numbers are platform-defined.

On RV32, mhpmcounter24h provides access to the upper 32 bits.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter24 is determined by mhpmevent24; check the event-selector configuration first.
- S/U-mode reads of the read-only hpmcounter24 shadow are controlled by mcounteren.HPM24; U-mode additionally requires scounteren.HPM24.
- On RV32, mhpmcounter24h accesses bits 63:32 of mhpmcounter24.

Risk Checks Before Writing

- A write to mhpmcounter24 takes effect after the writing instruction has otherwise completed and changes the current count.
- When mcountinhibit.HPM24 is set, the counter does not increment; that bit controls incrementing, not accessibility.

Put It Back Into A Real Flow

Configure mhpmevent24 to select the platform-defined event to count.

Use mcountinhibit.HPM24 when needed to control the counting window.

Read mhpmcounter24 and, on RV32, mhpmcounter24h to obtain the event count with up to 64 bits of precision.

FAQ

Can mhpmcounter24 be accessed from any privilege level?

No. The CSR table lists mhpmcounter24 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter24 view: S/U-mode reads are controlled by mcounteren.HPM24, and U-mode reads are additionally controlled by scounteren.HPM24. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter24 related to hpmcounter24?

mhpmcounter24 is the machine read/write counter; hpmcounter24 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM24, and U-mode reads are additionally controlled by scounteren.HPM24.