RISC-V mhpmcounter27 CSR Register

Address 0xB1BPrivilege MachineAccess RW / up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter27 at 0xB1B is machine hardware performance-monitor counter 27, a WARL counter with up to 64 bits of precision for the platform-defined event selected by mhpmevent27.

Related Search Terms

mhpmcounter27 CSR mhpmcounter27 0xB1B HPM counter 27 mhpmevent27 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter27 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the platform-defined event selected by mhpmevent27. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent27 read-only zero.

COUNT (bits 63:0) — Machine HPM count for the platform-defined event selected by mhpmevent27. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent27 read-only zero.

What This Field Controls

- Machine HPM count for the platform-defined event selected by mhpmevent27. COUNT is a WARL field with up to 64 bits of precision on RV32 and RV64; a legal implementation may make both this counter and mhpmevent27 read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter27 is machine HPM counter 27. It does not define event meaning by itself; it counts the platform-defined event currently selected by mhpmevent27 with up to 64 bits of precision.

The official Machine HPM mechanism defines mhpmcounter27 as a WARL counter with up to 64 bits of precision.

mhpmevent27 selects the event; event numbers are platform-defined.

On RV32, mhpmcounter27h provides access to the upper 32 bits.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter27 is determined by mhpmevent27; check the event-selector configuration first.
- S/U-mode reads of the read-only hpmcounter27 shadow are controlled by mcounteren.HPM27; U-mode additionally requires scounteren.HPM27.
- On RV32, mhpmcounter27h accesses bits 63:32 of mhpmcounter27.

Risk Checks Before Writing

- A write to mhpmcounter27 takes effect after the writing instruction has otherwise completed and changes the current count.
- When mcountinhibit.HPM27 is set, the counter does not increment; that bit controls incrementing, not accessibility.

Put It Back Into A Real Flow

Configure mhpmevent27 to select the platform-defined event to count.

Use mcountinhibit.HPM27 when needed to control the counting window.

Read mhpmcounter27 and, on RV32, mhpmcounter27h to obtain the event count with up to 64 bits of precision.

FAQ

Can mhpmcounter27 be accessed from any privilege level?

No. The CSR table lists mhpmcounter27 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter27 view: S/U-mode reads are controlled by mcounteren.HPM27, and U-mode reads are additionally controlled by scounteren.HPM27. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter27 related to hpmcounter27?

mhpmcounter27 is the machine read/write counter; hpmcounter27 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM27, and U-mode reads are additionally controlled by scounteren.HPM27.