Can mhpmcounter28h be accessed from any privilege level?
No. It is a Machine-mode CSR that exists only on RV32.
CSR Bit Fields
RISC-V mhpmcounter28h CSR Register
Address 0xB9CPrivilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs
mhpmcounter28h at 0xB9C is an RV32-only Machine high-half CSR, reading and writing mhpmcounter28[63:32].
Bit Overview
Hover for details · Click to jumpbit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map
Understand mhpmcounter28h By Bit Fields
0 key fields
Official Basis & Search Notes
mhpmcounter28h is an RV32 Machine high-half CSR for reading and writing mhpmcounter28[63:32]; it is not a separate counter.
This CSR exists only on RV32 and accesses mhpmcounter28[63:32].
The parent is a WARL counter supporting up to 64 bits of precision; events and implemented count/width are platform-defined.
A legal implementation may make the parent and mhpmevent28 read-only zero; mcountinhibit.HPM28 only inhibits incrementing.
What To Check First When Reading This CSR
- - mhpmcounter28h is provided only on RV32 as bits 63:32 of mhpmcounter28; this CSR does not exist on RV64.
- - The implemented counter count, width, and event set are platform-specific.
- - A legal implementation may make both mhpmcounter28 and mhpmevent28 read-only zero; mcountinhibit.HPM28 controls only whether the parent counter increments, not accessibility.
Risk Checks Before Writing
- - On RV32, writing mhpmcounter28h changes only bits 63:32 of its parent mhpmcounter28; the parent counter is WARL and supports up to 64 bits of precision.
Put It Back Into A Real Flow
1
Confirm that the needed counter is implemented.
2
On RV32, use mhpmcounter28h to access mhpmcounter28[63:32].
3
Interpret the parent counter using the platform-defined event in mhpmevent28.
FAQ
Is mhpmcounter28h a separate counter?
No. It is only the RV32 access CSR for the upper 32 bits of mhpmcounter28.