RISC-V mhpmcounter28 CSR Register

Address 0xB1CPrivilege MachineAccess RW / up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter28 at 0xB1C is machine hardware performance-monitor counter 28, a WARL counter with up to 64 bits of precision for the platform-defined event selected by mhpmevent28.

Related Search Terms

mhpmcounter28 CSR mhpmcounter28 0xB1C HPM counter 28 mhpmevent28 event machine performance counter up to 64-bit precision

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter28 By Bit Fields

1 key fields

63:0

COUNT

On RV64 only, reads and writes the complete Machine HPM count for the platform-defined event selected by mhpmevent28; this WARL counter supports up to 64 bits of precision.

COUNT (bits 63:0) — On RV64 only, reads and writes the complete Machine HPM count for the platform-defined event selected by mhpmevent28; this WARL counter supports up to 64 bits of precision.

What This Field Controls

- On RV64 only, reads and writes the complete Machine HPM count for the platform-defined event selected by mhpmevent28; this WARL counter supports up to 64 bits of precision.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter28 is machine HPM counter 28. It does not define event meaning by itself; it counts the platform-defined event currently selected by mhpmevent28 with up to 64 bits of precision.

The official Machine HPM mechanism defines mhpmcounter28 as a WARL counter with up to 64 bits of precision.

mhpmevent28 selects the event; event numbers are platform-defined.

On RV32, mhpmcounter28h provides access to the upper 32 bits.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter28 is determined by mhpmevent28; check the event-selector configuration first.
- S/U-mode reads of the read-only hpmcounter28 shadow are controlled by mcounteren.HPM28; U-mode additionally requires scounteren.HPM28.
- On RV32, mhpmcounter28h accesses bits 63:32 of mhpmcounter28.

Risk Checks Before Writing

- A write to mhpmcounter28 takes effect after the writing instruction has otherwise completed and changes the current count.
- When mcountinhibit.HPM28 is set, the counter does not increment; that bit controls incrementing, not accessibility.

Put It Back Into A Real Flow

Configure mhpmevent28 to select the platform-defined event to count.

Use mcountinhibit.HPM28 when needed to control the counting window.

Read mhpmcounter28 and, on RV32, mhpmcounter28h to obtain the event count with up to 64 bits of precision.

FAQ

Can mhpmcounter28 be accessed from any privilege level?

No. The CSR table lists mhpmcounter28 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter28 view: S/U-mode reads are controlled by mcounteren.HPM28, and U-mode reads are additionally controlled by scounteren.HPM28. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter28 related to hpmcounter28?

mhpmcounter28 is the machine read/write counter; hpmcounter28 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM28, and U-mode reads are additionally controlled by scounteren.HPM28.