RISC-V mhpmcounter4 CSR Register

Address 0xB04Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter4 at 0xB04 is machine hardware performance-monitor counter 4, with up to 64 bits of precision for the event selected by mhpmevent4.

Related Search Terms

mhpmcounter4 CSR mhpmcounter4 0xB04 HPM counter 4 mhpmevent4 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter4 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent4; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent4 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent4; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent4 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent4; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent4 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter4 is machine HPM counter 4. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent4.

The official machine HPM mechanism defines mhpmcounter4 as a WARL counter with up to 64 bits of precision.

mhpmevent4 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter4h accesses bits 63:32; a legal implementation may make both mhpmcounter4 and mhpmevent4 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter4 is selected by mhpmevent4; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter4 view are controlled by mcounteren.HPM4; U-mode is additionally controlled by scounteren.HPM4.
- On RV32, mhpmcounter4h accesses bits 63:32 of mhpmcounter4.

Risk Checks Before Writing

- Writing mhpmcounter4 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM4 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent4 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent4 to select the platform-defined event to count.

Set mcountinhibit.HPM4 when needed to stop mhpmcounter4 from incrementing.

Read mhpmcounter4; on RV32, also read mhpmcounter4h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter4 be accessed from any privilege level?

No. The CSR table lists mhpmcounter4 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter4 view: S/U-mode reads are controlled by mcounteren.HPM4, and U-mode reads are additionally controlled by scounteren.HPM4. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter4 related to hpmcounter4?

mhpmcounter4 is the machine read/write counter; hpmcounter4 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM4, and U-mode reads are additionally controlled by scounteren.HPM4.