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CSR Bit Fields

RISC-V mhpmcounter5 CSR Register

Address 0xB05Privilege MachineAccess RW / 64Machine counters and performance-monitoring CSRs

mhpmcounter5 at 0xB05 is machine hardware performance-monitor counter 5, a 64-bit counter for the event selected by mhpmevent5.

Related Search Terms
mhpmcounter5 CSRmhpmcounter5 0xB05HPM counter 5mhpmevent5 eventmachine performance counter64-bit count
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
COUNT63:0RW
Field Map

Understand mhpmcounter5 By Bit Fields

1 key fields
63:0

COUNT

RW

64-bit machine HPM count for the event selected by mhpmevent5; an unimplemented counter may read as zero.

COUNT (bits 63:0) — 64-bit machine HPM count for the event selected by mhpmevent5; an unimplemented counter may read as zero.

What This Field Controls

  • - 64-bit machine HPM count for the event selected by mhpmevent5; an unimplemented counter may read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter5 is machine HPM counter 5. It does not define event meaning by itself; it counts the platform-defined event currently selected by mhpmevent5.

The official Machine HPM mechanism provides mhpmcounter5 as a writable machine counter.
mhpmevent5 selects the event; event numbers are platform-defined.
On RV32, mhpmcounter5h provides access to the upper 32 bits.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

  • - The event source for mhpmcounter5 is determined by mhpmevent5; check the event-selector configuration first.
  • - Accessibility of the lower-privilege shadow hpmcounter5 is controlled by mcounteren/scounteren or relevant delegation mechanisms.
  • - On RV32, mhpmcounter5h accesses bits 63:32 of mhpmcounter5.

Risk Checks Before Writing

  • - Writing mhpmcounter5 changes the current counter value and should usually be done only during initialization, sample reset, or overflow handling.
  • - Use mcountinhibit.HPM5 or event/mode-filtering controls to stop counting rather than writing unknown event encodings.
  • - Multi-hart or platform sharing details must come from target implementation documentation.

Put It Back Into A Real Flow

1

Configure mhpmevent5 to select the platform-defined event to count.

2

Use mcountinhibit.HPM5 or xINH bits when needed to control the counting window.

3

Read mhpmcounter5 and, on RV32, mhpmcounter5h to obtain the 64-bit event count.

FAQ

Can mhpmcounter5 be accessed from any privilege level?

No. The official CSR table lists mhpmcounter5 as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

How is mhpmcounter5 related to hpmcounter5?

mhpmcounter5 is the machine readable/writable view; hpmcounter5 is the corresponding lower-privilege counter view, and its readability is controlled by counteren or delegation mechanisms.