RISC-V mhpmcounter5 CSR Register

Address 0xB05Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter5 at 0xB05 is machine hardware performance-monitor counter 5, with up to 64 bits of precision for the event selected by mhpmevent5.

Related Search Terms

mhpmcounter5 CSR mhpmcounter5 0xB05 HPM counter 5 mhpmevent5 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter5 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent5; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent5 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent5; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent5 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent5; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent5 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter5 is machine HPM counter 5. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent5.

The official machine HPM mechanism defines mhpmcounter5 as a WARL counter with up to 64 bits of precision.

mhpmevent5 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter5h accesses bits 63:32; a legal implementation may make both mhpmcounter5 and mhpmevent5 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter5 is selected by mhpmevent5; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter5 view are controlled by mcounteren.HPM5; U-mode is additionally controlled by scounteren.HPM5.
- On RV32, mhpmcounter5h accesses bits 63:32 of mhpmcounter5.

Risk Checks Before Writing

- Writing mhpmcounter5 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM5 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent5 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent5 to select the platform-defined event to count.

Set mcountinhibit.HPM5 when needed to stop mhpmcounter5 from incrementing.

Read mhpmcounter5; on RV32, also read mhpmcounter5h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter5 be accessed from any privilege level?

No. The CSR table lists mhpmcounter5 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter5 view: S/U-mode reads are controlled by mcounteren.HPM5, and U-mode reads are additionally controlled by scounteren.HPM5. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter5 related to hpmcounter5?

mhpmcounter5 is the machine read/write counter; hpmcounter5 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM5, and U-mode reads are additionally controlled by scounteren.HPM5.