RISC-V mhpmcounter6 CSR Register

Address 0xB06Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter6 at 0xB06 is machine hardware performance-monitor counter 6, with up to 64 bits of precision for the event selected by mhpmevent6.

Related Search Terms

mhpmcounter6 CSR mhpmcounter6 0xB06 HPM counter 6 mhpmevent6 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter6 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent6; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent6 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent6; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent6 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent6; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent6 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter6 is machine HPM counter 6. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent6.

The official machine HPM mechanism defines mhpmcounter6 as a WARL counter with up to 64 bits of precision.

mhpmevent6 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter6h accesses bits 63:32; a legal implementation may make both mhpmcounter6 and mhpmevent6 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter6 is selected by mhpmevent6; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter6 view are controlled by mcounteren.HPM6; U-mode is additionally controlled by scounteren.HPM6.
- On RV32, mhpmcounter6h accesses bits 63:32 of mhpmcounter6.

Risk Checks Before Writing

- Writing mhpmcounter6 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM6 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent6 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent6 to select the platform-defined event to count.

Set mcountinhibit.HPM6 when needed to stop mhpmcounter6 from incrementing.

Read mhpmcounter6; on RV32, also read mhpmcounter6h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter6 be accessed from any privilege level?

No. The CSR table lists mhpmcounter6 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter6 view: S/U-mode reads are controlled by mcounteren.HPM6, and U-mode reads are additionally controlled by scounteren.HPM6. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter6 related to hpmcounter6?

mhpmcounter6 is the machine read/write counter; hpmcounter6 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM6, and U-mode reads are additionally controlled by scounteren.HPM6.