RISC-V midelegh CSR Register

Address 0x313Privilege MachineAccess RW / RV32 high-half / 32-bitMachine delegation, environment-configuration, and state-enable CSRs

midelegh is the RV32 high-half companion for machine interrupt delegation state.

Related Search Terms

midelegh CSR midelegh 0x313 RV32 mideleg high interrupt delegation high machine delegation high RISC-V midelegh

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32VALUE31:0RW

Field Map

Understand midelegh By Bit Fields

1 key fields

31:0

VALUE

Full register value of midelegh; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

VALUE (bits 31:0) — Full register value of midelegh; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

What This Field Controls

- Full register value of midelegh; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

Common Values

0Not delegated

The high-half corresponding interrupt code is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The high-half corresponding interrupt code is delegated to S-mode when it occurs below M-mode.

Official Basis & Search Notes

midelegh is a RW CSR in machine delegation, environment-configuration, and state-enable csrs at 0x313. Check privilege and implemented extensions before interpreting its bit fields.

midelegh address, lowest access privilege, and access class are checked against the official CSR table: 0x313, Machine, RW.

Read it as part of machine delegation, environment-configuration, and state-enable csrs before interpreting the bit-field table on this page.

Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.

RISC-V Privileged Architecture Manual RISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

- First confirm that the current hart implements midelegh; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- Use address 0x313 and the lowest access privilege (Machine) to decide whether software may read it directly.
- Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

- Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
- Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

During initialization or the relevant privileged flow, software reads midelegh to observe the current state.

Modify only the target fields while preserving all other bits.

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can midelegh be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records midelegh as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing midelegh?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.