RISC-V midelegh CSR Register

Address 0x313Privilege MachineAccess RW / RV32 high-half / 32-bitMachine delegation, environment-configuration, and state-enable CSRs

midelegh at 0x313 is the AIA-defined RV32 high-half CSR for mideleg, aliasing interrupt delegation bits mideleg[63:32] of the 64-bit mideleg register.

Related Search Terms

midelegh CSR midelegh 0x313 AIA midelegh RV32 mideleg high mideleg 63:32 interrupt delegation high

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Field Map

Understand midelegh By Bit Fields

1 key fields

31:0 (aliases mideleg[63:32])

ID[63:32]

WARL

Upper 32 interrupt delegation bits of mideleg, matching the widened mip/mie interrupt-bit layout. AIA widens mideleg to 64 bits and provides midelegh on RV32 for the upper half. Supported bits are implementation-defined and discovered by writing ones and reading back.

ID[63:32] (bits 31:0 (aliases mideleg[63:32])) — Upper 32 interrupt delegation bits of mideleg, matching the widened mip/mie interrupt-bit layout. AIA widens mideleg to 64 bits and provides midelegh on RV32 for the upper half. Supported bits are implementation-defined and discovered by writing ones and reading back.

What This Field Controls

- Upper 32 interrupt delegation bits of mideleg, matching the widened mip/mie interrupt-bit layout. AIA widens mideleg to 64 bits and provides midelegh on RV32 for the upper half. Supported bits are implementation-defined and discovered by writing ones and reading back.

Common Values

0Disabled

The corresponding cause is not delegated to S-mode by this bit; if it occurs below M-mode and no other delegation path applies, it is taken by the M-mode trap handler.

1Enabled

The corresponding cause is delegated to the S-mode trap handler when it occurs in S-mode or U-mode; traps from M-mode are not delegated downward.

Official Basis & Search Notes

midelegh is AIA's RV32 access window for the upper half of mideleg. It serves the 64-bit interrupt delegation bitmap; setting a bit delegates the corresponding interrupt for S/U-mode paths to S-mode, not downward from M-mode.

AIA widens mideleg to 64 bits and adds midelegh on RV32 to access bits 63:32.

midelegh applies only with S-mode, and supported bits are an implementation subset.

Delegated interrupts are masked at M-mode and visible through the S-mode sip/sie view.

RISC-V Advanced Interrupt Architecture v1.0, CSRs Added to Harts RISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

- midelegh is an AIA-added RV32-only high-half CSR at 0x313 with 32-bit width.
- It is the access window for mideleg[63:32] only in the relevant AIA configuration with S-mode.
- Supported high-numbered interrupt delegation bits are implementation-defined and discovered by writing ones and reading back.

Risk Checks Before Writing

- Do not treat midelegh as a generic CSR from the base privileged table; it comes from AIA widening mideleg to 64 bits.
- Delegated interrupts are masked at M-mode and become visible through the S-mode path; nondelegated interrupts remain on the M-mode path.

Put It Back Into A Real Flow

RV32 M-mode software first confirms AIA/S-mode support, then reads midelegh.

Set only high-numbered interrupt bits that should be delegated and read back as supported.

Validate delegation through interrupt delivery and sip/sie visibility.

FAQ

Can midelegh be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records midelegh as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing midelegh?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.