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CSR Bit Fields

RISC-V mstateen0 CSR Register

Address 0x30CPrivilege MachineAccess RW / 64-bit on RV64; RV32 accesses the low/high halves through mstateen0 and mstateen0hMachine delegation, environment-configuration, and state-enable CSRs

Machine State Enable 0 register; controls access below M-mode to stateen, envcfg, AIA/IMSIC, CSR-indirection, context, FCSR, JVT, custom state, and related extension state.

Related Search Terms
mstateen0 CSRmstateen0 0x30Cmstateen0 SE0 ENVCFGmstateen0 AIA IMSICmstateen0 FCSR JVTSmstateen
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
SE063WARLC0WARL
Field Map

Understand mstateen0 By Bit Fields

13 key fields
63

SE0

WARL

Controls access to hstateen0, hstateen0h, and sstateen0. May be RO0 only if H is absent and every bit of the matching sstateen0 is RO0.

SE0 (bit 63) — Controls access to hstateen0, hstateen0h, and sstateen0. May be RO0 only if H is absent and every bit of the matching sstateen0 is RO0.

What This Field Controls

  • - Controls access to hstateen0, hstateen0h, and sstateen0. May be RO0 only if H is absent and every bit of the matching sstateen0 is RO0.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

62

ENVCFG

WARL

Controls access to henvcfg, henvcfgh, and senvcfg.

ENVCFG (bit 62) — Controls access to henvcfg, henvcfgh, and senvcfg.

What This Field Controls

  • - Controls access to henvcfg, henvcfgh, and senvcfg.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

60

CSRIND

WARL/RO0

Controls access to siselect, sireg*, vsiselect, and vsireg* CSRs provided by Sscsrind extensions.

CSRIND (bit 60) — Controls access to siselect, sireg*, vsiselect, and vsireg* CSRs provided by Sscsrind extensions.

What This Field Controls

  • - Controls access to siselect, sireg*, vsiselect, and vsireg* CSRs provided by Sscsrind extensions.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

59

AIA

WARL/RO0

Controls access to Ssaia state not controlled by CSRIND or IMSIC.

AIA (bit 59) — Controls access to Ssaia state not controlled by CSRIND or IMSIC.

What This Field Controls

  • - Controls access to Ssaia state not controlled by CSRIND or IMSIC.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

58

IMSIC

WARL/RO0

Controls access to IMSIC state, including stopei and vstopei, provided by Ssaia.

IMSIC (bit 58) — Controls access to IMSIC state, including stopei and vstopei, provided by Ssaia.

What This Field Controls

  • - Controls access to IMSIC state, including stopei and vstopei, provided by Ssaia.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

57

CONTEXT

WARL/RO0

Controls access to scontext and hcontext CSRs provided by Sdtrig.

CONTEXT (bit 57) — Controls access to scontext and hcontext CSRs provided by Sdtrig.

What This Field Controls

  • - Controls access to scontext and hcontext CSRs provided by Sdtrig.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

56

P1P13

WARL/RO0

Controls access to hedelegh introduced by Privileged Specification Version 1.13.

P1P13 (bit 56) — Controls access to hedelegh introduced by Privileged Specification Version 1.13.

What This Field Controls

  • - Controls access to hedelegh introduced by Privileged Specification Version 1.13.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

55

SRMCFG

WARL/RO0

Controls access to srmcfg introduced by Ssqosid.

SRMCFG (bit 55) — Controls access to srmcfg introduced by Ssqosid.

What This Field Controls

  • - Controls access to srmcfg introduced by Ssqosid.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

54

CTR

WARL/RO0

Controls access to CTR register state from privilege modes less privileged than M-mode when Smctr/Ssctr CTR state exists.

CTR (bit 54) — Controls access to CTR register state from privilege modes less privileged than M-mode when Smctr/Ssctr CTR state exists.

What This Field Controls

  • - Controls access to CTR register state from privilege modes less privileged than M-mode when Smctr/Ssctr CTR state exists.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

2

JVT

WARL/RO0

Controls access to the jvt CSR provided by Zcmt.

JVT (bit 2) — Controls access to the jvt CSR provided by Zcmt.

What This Field Controls

  • - Controls access to the jvt CSR provided by Zcmt.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

1

FCSR

WARL/RO0

Controls access to fcsr when floating-point instructions use x registers under Zfinx-related extensions; RO0 when misa.F=1.

FCSR (bit 1) — Controls access to fcsr when floating-point instructions use x registers under Zfinx-related extensions; RO0 when misa.F=1.

What This Field Controls

  • - Controls access to fcsr when floating-point instructions use x registers under Zfinx-related extensions; RO0 when misa.F=1.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

0

C

WARL

Controls access to any and all custom state; the C bit itself remains a standard CSR field.

C (bit 0) — Controls access to any and all custom state; the C bit itself remains a standard CSR field.

What This Field Controls

  • - Controls access to any and all custom state; the C bit itself remains a standard CSR field.

Common Values

0Disabled

Privilege modes below M cannot access the controlled state; depending on context, access raises an illegal-instruction or virtual-instruction exception, or related implicit state updates are prevented.

1Enabled

Allows privilege modes below M to access the controlled state, still subject to matching hstateen/sstateen or other architectural controls.

61, 53:48, 47:3

WPRI

WPRI

Reserved/WPRI fields in the mstateen0 layout.

WPRI (bits 61, 53:48, 47:3) — Reserved/WPRI fields in the mstateen0 layout.

What This Field Controls

  • - Reserved/WPRI fields in the mstateen0 layout.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mstateen0 is an M-mode gate for extension state. It lets machine-level software decide whether lower privilege modes may access stateen/envcfg, AIA/IMSIC, CSR-indirection, debug context, JVT, FCSR, custom state, and related resources.

Standard-defined stateen bits are WARL, and bits for unimplemented controlled state read as zero.
Writable mstateen bits reset to zero; after M-mode software enables them, it must initialize matching hstateen/sstateen CSRs.
Bit 63 (SE0) controls access to the matching sstateen0/hstateen0 CSRs.
RISC-V Privileged Architecture Manual v20260120, CSR tableRISC-V Privileged Architecture Manual v20260120, Smstateen/SsstateenRISC-V Privileged Architecture Manual v20260120, Smctr/Ssctr

What To Check First When Reading This CSR

  • - Smstateen adds mstateen0 as a 64-bit machine-level state-enable CSR on RV64; RV32 uses mstateen0h for bits 63:32.
  • - Each standard-defined stateen bit is WARL and may be read-only zero or read-only one.
  • - If a controlled state is not implemented, its stateen bit is read-only zero. Writable mstateen bits reset to zero.

Risk Checks Before Writing

  • - Clearing a stateen bit prevents less-privileged access to the controlled state and can make explicit access trap or implicit state update fail.
  • - After setting any writable mstateen bit to one, machine-level software must initialize matching hstateen CSRs if they exist and matching sstateen CSRs for bits that have them.
  • - Preserve WPRI fields and read back WARL bits to learn the implemented access-control subset.

Put It Back Into A Real Flow

1

Start from reset state where writable mstateen bits are zero.

2

Enable only the extension state that lower privilege modes are prepared to save, restore, or emulate.

3

Initialize matching hstateen and sstateen CSRs before exposing the controlled state to lower privilege software.