RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V mstateen3 CSR Register

Address 0x30FPrivilege MachineAccess RW / 64-bit on RV64; RV32 accesses the low/high halves through mstateen3 and mstateen3hMachine delegation, environment-configuration, and state-enable CSRs

mstateen3 at 0x30F is an M-mode state-enable CSR defined by Smstateen; bit 63 controls lower-privilege access to the matching hstateen3/sstateen3 CSRs.

Related Search Terms
mstateen3 CSRmstateen3 0x30Fmstateen3 SE3mstateen3 bit 63Smstateen mstateen3hstateen3 sstateen3
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
SE363WARLState bits / reserved62:0WARL/RO0
Field Map

Understand mstateen3 By Bit Fields

2 key fields
63

SE3

WARL

Controls access to hstateen3, hstateen3h on RV32, and sstateen3. May be RO0 only if H is absent and the matching sstateen3 CSR is all read-only zero.

SE3 (bit 63) — Controls access to hstateen3, hstateen3h on RV32, and sstateen3. May be RO0 only if H is absent and the matching sstateen3 CSR is all read-only zero.

What This Field Controls

  • - Controls access to hstateen3, hstateen3h on RV32, and sstateen3. May be RO0 only if H is absent and the matching sstateen3 CSR is all read-only zero.

Common Values

0Disabled

Privilege modes below M cannot access the matching stateen CSR controlled by this bit; access normally raises an illegal-instruction or virtual-instruction exception. Only when this SE bit is permitted to be read-only zero does M-mode software need to emulate S-mode reads and writes to the affected sstateen CSR.

1Enabled

Allows privilege modes below M to access the matching hstateen/sstateen CSR, still subject to the corresponding hstateen bit and other architectural controls.

62:0

State bits / reserved

WARL/RO0

These bits can carry the same state-access controls as bits defined in the matching sstateen3 CSR. Each standard-defined stateen bit is WARL; bits for unimplemented state and reserved bits not yet defined read as zero, and software must not infer undefined functions from bit positions.

State bits / reserved (bits 62:0) — These bits can carry the same state-access controls as bits defined in the matching sstateen3 CSR. Each standard-defined stateen bit is WARL; bits for unimplemented state and reserved bits not yet defined read as zero, and software must not infer undefined functions from bit positions.

What This Field Controls

  • - These bits can carry the same state-access controls as bits defined in the matching sstateen3 CSR. Each standard-defined stateen bit is WARL; bits for unimplemented state and reserved bits not yet defined read as zero, and software must not infer undefined functions from bit positions.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

Bit 63 of mstateen3 is SE3, which lets M-mode control whether lower privilege modes may access matching hstateen3/sstateen3 CSRs. Lower bits can carry matching controls for officially defined sstateen3 state bits; unimplemented state and undefined reserved bits read as zero.

A stateen CSR controls access below its own privilege level, not access by that same level.
SE3 is WARL and may be RO0 only when H is absent and the matching sstateen3 CSR is all read-only zero.
Bits for undefined or unimplemented state read as zero; software must not infer future extension behavior from reserved bits.
RISC-V Privileged Architecture Manual v20260120, CSR tableRISC-V Privileged Architecture Manual v20260120, Smstateen/Ssstateen

What To Check First When Reading This CSR

  • - mstateen3 belongs to Smstateen; access traps as illegal instruction if the extension is absent or privilege is insufficient.
  • - Standard-defined stateen bits are WARL; bits for unimplemented controlled state and undefined reserved bits read as zero.
  • - Bit 63 controls access to matching hstateen3/sstateen3 CSRs, not access by M-mode itself.

Risk Checks Before Writing

  • - Modify only target bits that are officially defined and implemented as writable; reserved bits read as zero and must not be used for private software meaning.
  • - If M-mode sets writable mstateen bits to one, it must initialize matching writable hstateen/sstateen bits as specified.

Put It Back Into A Real Flow

1

M-mode first reads mstateen3 to determine whether SE3 and any officially defined state bits are writable, and whether reserved bits read as zero.

2

If lower privilege modes need access to matching stateen3 CSRs, modify SE3; if defined state is enabled, modify only the corresponding officially defined bits.

3

Then initialize matching writable hstateen/sstateen bits so uninitialized state is not exposed to lower privilege modes.

FAQ

What does bit 63 of mstateen3 control?

It controls lower-privilege access to hstateen3, hstateen3h on RV32, and sstateen3.

Can other mstateen3 bits be used as software-private bits?

No. Currently undefined or reserved bits read as zero by the official specification and may later be assigned meaning by standard extensions.