RISC-V pmpcfg2 CSR Register

PMP entry 8 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr8 may still be locked by a later locked TOR entry.

PMP entry 8 is locked; writes to pmp8cfg and pmpaddr8 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr7 is also locked.

PMP entry 8 is disabled and matches no addresses.

PMP entry 8 uses top-of-range matching; the upper bound comes from pmpaddr8, and the lower bound comes from pmpaddr7.

PMP entry 8 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 8 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr8.

PMP entry 8 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 8 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 8 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 8 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 8 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 8 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 9 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr9 may still be locked by a later locked TOR entry.

PMP entry 9 is locked; writes to pmp9cfg and pmpaddr9 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr8 is also locked.

PMP entry 9 is disabled and matches no addresses.

PMP entry 9 uses top-of-range matching; the upper bound comes from pmpaddr9, and the lower bound comes from pmpaddr8.

PMP entry 9 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 9 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr9.

PMP entry 9 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 9 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 9 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 9 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 9 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 9 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 10 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr10 may still be locked by a later locked TOR entry.

PMP entry 10 is locked; writes to pmp10cfg and pmpaddr10 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr9 is also locked.

PMP entry 10 is disabled and matches no addresses.

PMP entry 10 uses top-of-range matching; the upper bound comes from pmpaddr10, and the lower bound comes from pmpaddr9.

PMP entry 10 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 10 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr10.

PMP entry 10 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 10 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 10 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 10 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 10 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 10 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 11 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr11 may still be locked by a later locked TOR entry.

PMP entry 11 is locked; writes to pmp11cfg and pmpaddr11 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr10 is also locked.

PMP entry 11 is disabled and matches no addresses.

PMP entry 11 uses top-of-range matching; the upper bound comes from pmpaddr11, and the lower bound comes from pmpaddr10.

PMP entry 11 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 11 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr11.

PMP entry 11 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 11 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 11 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 11 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 11 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 11 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 12 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr12 may still be locked by a later locked TOR entry.

PMP entry 12 is locked; writes to pmp12cfg and pmpaddr12 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr11 is also locked.

PMP entry 12 is disabled and matches no addresses.

PMP entry 12 uses top-of-range matching; the upper bound comes from pmpaddr12, and the lower bound comes from pmpaddr11.

PMP entry 12 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 12 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr12.

PMP entry 12 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 12 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 12 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 12 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 12 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 12 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 13 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr13 may still be locked by a later locked TOR entry.

PMP entry 13 is locked; writes to pmp13cfg and pmpaddr13 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr12 is also locked.

PMP entry 13 is disabled and matches no addresses.

PMP entry 13 uses top-of-range matching; the upper bound comes from pmpaddr13, and the lower bound comes from pmpaddr12.

PMP entry 13 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 13 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr13.

PMP entry 13 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 13 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 13 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 13 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 13 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 13 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 14 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr14 may still be locked by a later locked TOR entry.

PMP entry 14 is locked; writes to pmp14cfg and pmpaddr14 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr13 is also locked.

PMP entry 14 is disabled and matches no addresses.

PMP entry 14 uses top-of-range matching; the upper bound comes from pmpaddr14, and the lower bound comes from pmpaddr13.

PMP entry 14 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 14 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr14.

PMP entry 14 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 14 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 14 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 14 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 14 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 14 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 15 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr15 may still be locked by a later locked TOR entry.

PMP entry 15 is locked; writes to pmp15cfg and pmpaddr15 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr14 is also locked.

PMP entry 15 is disabled and matches no addresses.

PMP entry 15 uses top-of-range matching; the upper bound comes from pmpaddr15, and the lower bound comes from pmpaddr14.

PMP entry 15 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 15 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr15.

PMP entry 15 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 15 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 15 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 15 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 15 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 15 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.