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CSR Bit Fields

RISC-V mseccfg CSR Register

Address 0x747Privilege MachineAccess RW / 64-bitMachine security CSRs

Optional 64-bit machine security configuration CSR; it exists only when an extension adds a field.

Related Search Terms
mseccfg CSRmseccfg 0x747MMLMMWPRLB
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
WPRI63:48WPRIMML0WARL/Smepmp
Field Map

Understand mseccfg By Bit Fields

11 key fields
63:48

WPRI

WPRI

Reserved.

WPRI (bits 63:48) — Reserved.

What This Field Controls

  • - Reserved.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

47:34

WPRI

WPRI

Reserved.

WPRI (bits 47:34) — Reserved.

What This Field Controls

  • - Reserved.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

33:32

PMM

WARL/Smmpm/RV64

Smmpm M-mode pointer masking; read-only zero without Smmpm or on RV32.

PMM (bits 33:32) — Smmpm M-mode pointer masking; read-only zero without Smmpm or on RV32.

What This Field Controls

  • - Smmpm M-mode pointer masking; read-only zero without Smmpm or on RV32.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

31:11

WPRI

WPRI

Reserved.

WPRI (bits 31:11) — Reserved.

What This Field Controls

  • - Reserved.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

10

MLPE

Zicfilp

When 1, enables Zicfilp in M-mode; otherwise ELP is not updated and LPAD is a no-op.

MLPE (bit 10) — When 1, enables Zicfilp in M-mode; otherwise ELP is not updated and LPAD is a no-op.

What This Field Controls

  • - When 1, enables Zicfilp in M-mode; otherwise ELP is not updated and LPAD is a no-op.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

9

SSEED

Zkr/optional RO0

Controls S/HS read-write access to seed; read-only zero without Zkr or S-mode.

SSEED (bit 9) — Controls S/HS read-write access to seed; read-only zero without Zkr or S-mode.

What This Field Controls

  • - Controls S/HS read-write access to seed; read-only zero without Zkr or S-mode.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

8

USEED

Zkr/optional RO0

Controls U-mode read-write access to seed; read-only zero without Zkr or U-mode.

USEED (bit 8) — Controls U-mode read-write access to seed; read-only zero without Zkr or U-mode.

What This Field Controls

  • - Controls U-mode read-write access to seed; read-only zero without Zkr or U-mode.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

7:3

WPRI

WPRI

Reserved.

WPRI (bits 7:3) — Reserved.

What This Field Controls

  • - Reserved.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

2

RLB

WARL/Smepmp

Rule-locking bypass; when RLB is 0 and pmpcfg.L is 1 in any PMP entry, including a disabled entry, RLB remains 0 until PMP reset.

RLB (bit 2) — Rule-locking bypass; when RLB is 0 and pmpcfg.L is 1 in any PMP entry, including a disabled entry, RLB remains 0 until PMP reset.

What This Field Controls

  • - Rule-locking bypass; when RLB is 0 and pmpcfg.L is 1 in any PMP entry, including a disabled entry, RLB remains 0 until PMP reset.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

1

MMWP

WARL/Smepmp

M-mode allowlist policy; sticky until PMP reset and denies M-mode accesses without a matching rule.

MMWP (bit 1) — M-mode allowlist policy; sticky until PMP reset and denies M-mode accesses without a matching rule.

What This Field Controls

  • - M-mode allowlist policy; sticky until PMP reset and denies M-mode accesses without a matching rule.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

0

MML

WARL/Smepmp

Machine Mode Lockdown; sticky until PMP reset and changes PMP L-bit semantics.

MML (bit 0) — Machine Mode Lockdown; sticky until PMP reset and changes PMP L-bit semantics.

What This Field Controls

  • - Machine Mode Lockdown; sticky until PMP reset and changes PMP L-bit semantics.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

Optional 64-bit machine security configuration CSR; it exists only when an extension adds a field.

Collects machine-security controls from Smepmp, Zkr, Smmpm, and Zicfilp.
RISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - This CSR is reserved when no extension adds a field to it.
  • - Smepmp MML and MMWP cannot be cleared before a PMP reset once set.

Risk Checks Before Writing

  • - RLB weakens protection of locked PMP rules and should be avoided after normal boot operation.
  • - Honor extension conditions for read-only-zero fields.

Put It Back Into A Real Flow

1

Confirm required extensions.

2

Configure fields under locking and WARL rules.

3

Read back to determine accepted values.