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CSR Bit Fields

RISC-V pmpcfg0 CSR Register

Address 0x3A0Privilege MachineAccess Machine RW (all fields WARL/may be RO0) / MXLEN: 32 bits on RV32; 64 bits on RV64Machine physical memory protection CSRs

pmpcfg0 (0x3A0) is a machine PMP configuration CSR packing pmp0cfg-pmp3cfg on RV32 and pmp0cfg-pmp7cfg on RV64.

Related Search Terms
pmpcfg0 CSRpmpcfg0 0x3A0PMP R W XPMP A fieldPMP L bitPMP entries 0-7
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
pmp7cfg.L63WARL/may be RO0pmp0cfg.R0Collective WARL (R/W/X)
Field Map

Understand pmpcfg0 By Bit Fields

48 key fields
7

pmp0cfg.L

WARL/may be RO0

Lock bit for PMP entry 0. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp0cfg.L (bit 7) — Lock bit for PMP entry 0. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 0. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp0cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
6:5

pmp0cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp0cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp0cfg.reserved (bits 6:5) — Bits 6:5 of pmp0cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp0cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
4:3

pmp0cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 0. This field is WARL and may be implemented as read-only zero.

pmp0cfg.A (bits 4:3) — Address-matching mode for PMP entry 0. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 0. This field is WARL and may be implemented as read-only zero.

Common Values

pmp0cfg.A
0OFF

PMP entry 0 is disabled and matches no addresses.

1TOR

PMP entry 0 uses top-of-range matching; the upper bound comes from pmpaddr0, and the lower bound is zero.

2NA4

PMP entry 0 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 0 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr0.

↗Open Official Manual
2

pmp0cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp0cfg.X (bit 2) — X bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp0cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
1

pmp0cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp0cfg.W (bit 1) — W bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp0cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
0

pmp0cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp0cfg.R (bit 0) — R bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 0; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp0cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
15

pmp1cfg.L

WARL/may be RO0

Lock bit for PMP entry 1. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp1cfg.L (bit 15) — Lock bit for PMP entry 1. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 1. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp1cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
14:13

pmp1cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp1cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp1cfg.reserved (bits 14:13) — Bits 6:5 of pmp1cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp1cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12:11

pmp1cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 1. This field is WARL and may be implemented as read-only zero.

pmp1cfg.A (bits 12:11) — Address-matching mode for PMP entry 1. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 1. This field is WARL and may be implemented as read-only zero.

Common Values

pmp1cfg.A
0OFF

PMP entry 1 is disabled and matches no addresses.

1TOR

PMP entry 1 uses top-of-range matching; the upper bound comes from pmpaddr1, and the lower bound comes from pmpaddr0.

2NA4

PMP entry 1 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 1 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr1.

↗Open Official Manual
10

pmp1cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp1cfg.X (bit 10) — X bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp1cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
9

pmp1cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp1cfg.W (bit 9) — W bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp1cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
8

pmp1cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp1cfg.R (bit 8) — R bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 1; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp1cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
23

pmp2cfg.L

WARL/may be RO0

Lock bit for PMP entry 2. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp2cfg.L (bit 23) — Lock bit for PMP entry 2. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 2. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp2cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
22:21

pmp2cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp2cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp2cfg.reserved (bits 22:21) — Bits 6:5 of pmp2cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp2cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
20:19

pmp2cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 2. This field is WARL and may be implemented as read-only zero.

pmp2cfg.A (bits 20:19) — Address-matching mode for PMP entry 2. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 2. This field is WARL and may be implemented as read-only zero.

Common Values

pmp2cfg.A
0OFF

PMP entry 2 is disabled and matches no addresses.

1TOR

PMP entry 2 uses top-of-range matching; the upper bound comes from pmpaddr2, and the lower bound comes from pmpaddr1.

2NA4

PMP entry 2 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 2 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr2.

↗Open Official Manual
18

pmp2cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp2cfg.X (bit 18) — X bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp2cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
17

pmp2cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp2cfg.W (bit 17) — W bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp2cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
16

pmp2cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp2cfg.R (bit 16) — R bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 2; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp2cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
31

pmp3cfg.L

WARL/may be RO0

Lock bit for PMP entry 3. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp3cfg.L (bit 31) — Lock bit for PMP entry 3. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 3. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp3cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
30:29

pmp3cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp3cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp3cfg.reserved (bits 30:29) — Bits 6:5 of pmp3cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp3cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
28:27

pmp3cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 3. This field is WARL and may be implemented as read-only zero.

pmp3cfg.A (bits 28:27) — Address-matching mode for PMP entry 3. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 3. This field is WARL and may be implemented as read-only zero.

Common Values

pmp3cfg.A
0OFF

PMP entry 3 is disabled and matches no addresses.

1TOR

PMP entry 3 uses top-of-range matching; the upper bound comes from pmpaddr3, and the lower bound comes from pmpaddr2.

2NA4

PMP entry 3 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 3 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr3.

↗Open Official Manual
26

pmp3cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp3cfg.X (bit 26) — X bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp3cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
25

pmp3cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp3cfg.W (bit 25) — W bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp3cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
24

pmp3cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp3cfg.R (bit 24) — R bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 3; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp3cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
39

pmp4cfg.L

WARL/may be RO0

Lock bit for PMP entry 4. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp4cfg.L (bit 39) — Lock bit for PMP entry 4. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 4. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp4cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
38:37

pmp4cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp4cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp4cfg.reserved (bits 38:37) — Bits 6:5 of pmp4cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp4cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
36:35

pmp4cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 4. This field is WARL and may be implemented as read-only zero.

pmp4cfg.A (bits 36:35) — Address-matching mode for PMP entry 4. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 4. This field is WARL and may be implemented as read-only zero.

Common Values

pmp4cfg.A
0OFF

PMP entry 4 is disabled and matches no addresses.

1TOR

PMP entry 4 uses top-of-range matching; the upper bound comes from pmpaddr4, and the lower bound comes from pmpaddr3.

2NA4

PMP entry 4 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 4 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr4.

↗Open Official Manual
34

pmp4cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp4cfg.X (bit 34) — X bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp4cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
33

pmp4cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp4cfg.W (bit 33) — W bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp4cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
32

pmp4cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp4cfg.R (bit 32) — R bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 4; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp4cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
47

pmp5cfg.L

WARL/may be RO0

Lock bit for PMP entry 5. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp5cfg.L (bit 47) — Lock bit for PMP entry 5. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 5. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp5cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
46:45

pmp5cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp5cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp5cfg.reserved (bits 46:45) — Bits 6:5 of pmp5cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp5cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
44:43

pmp5cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 5. This field is WARL and may be implemented as read-only zero.

pmp5cfg.A (bits 44:43) — Address-matching mode for PMP entry 5. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 5. This field is WARL and may be implemented as read-only zero.

Common Values

pmp5cfg.A
0OFF

PMP entry 5 is disabled and matches no addresses.

1TOR

PMP entry 5 uses top-of-range matching; the upper bound comes from pmpaddr5, and the lower bound comes from pmpaddr4.

2NA4

PMP entry 5 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 5 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr5.

↗Open Official Manual
42

pmp5cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp5cfg.X (bit 42) — X bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp5cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
41

pmp5cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp5cfg.W (bit 41) — W bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp5cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
40

pmp5cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp5cfg.R (bit 40) — R bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 5; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp5cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
55

pmp6cfg.L

WARL/may be RO0

Lock bit for PMP entry 6. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp6cfg.L (bit 55) — Lock bit for PMP entry 6. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 6. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp6cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
54:53

pmp6cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp6cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp6cfg.reserved (bits 54:53) — Bits 6:5 of pmp6cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp6cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
52:51

pmp6cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 6. This field is WARL and may be implemented as read-only zero.

pmp6cfg.A (bits 52:51) — Address-matching mode for PMP entry 6. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 6. This field is WARL and may be implemented as read-only zero.

Common Values

pmp6cfg.A
0OFF

PMP entry 6 is disabled and matches no addresses.

1TOR

PMP entry 6 uses top-of-range matching; the upper bound comes from pmpaddr6, and the lower bound comes from pmpaddr5.

2NA4

PMP entry 6 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 6 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr6.

↗Open Official Manual
50

pmp6cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp6cfg.X (bit 50) — X bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp6cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
49

pmp6cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp6cfg.W (bit 49) — W bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp6cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
48

pmp6cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp6cfg.R (bit 48) — R bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 6; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp6cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
63

pmp7cfg.L

WARL/may be RO0

Lock bit for PMP entry 7. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp7cfg.L (bit 63) — Lock bit for PMP entry 7. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 7. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp7cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
62:61

pmp7cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp7cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp7cfg.reserved (bits 62:61) — Bits 6:5 of pmp7cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp7cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
60:59

pmp7cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 7. This field is WARL and may be implemented as read-only zero.

pmp7cfg.A (bits 60:59) — Address-matching mode for PMP entry 7. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 7. This field is WARL and may be implemented as read-only zero.

Common Values

pmp7cfg.A
0OFF

PMP entry 7 is disabled and matches no addresses.

1TOR

PMP entry 7 uses top-of-range matching; the upper bound comes from pmpaddr7, and the lower bound comes from pmpaddr6.

2NA4

PMP entry 7 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 7 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr7.

↗Open Official Manual
58

pmp7cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp7cfg.X (bit 58) — X bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp7cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
57

pmp7cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp7cfg.W (bit 57) — W bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp7cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
56

pmp7cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp7cfg.R (bit 56) — R bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 7; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp7cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
Official Basis & Search Notes

pmpcfg0 packs four 8-bit PMP configurations on RV32 and eight on RV64; each contains L, A, X, W, R, and two reserved zero bits.

The Machine ISA Physical Memory Protection CSRs subsection defines the address, MXLEN packing, M-mode-only access, and WARL/RO0 behavior.
A encodes OFF, TOR, NA4, or NAPOT; platform grain may make NA4 unselectable.
Base PMP and Smepmp with MML=1 interpret L/R/W/X differently, so field values must be read with mseccfg state.
RISC-V ISA Manual 2026-07-09 release - Machine ISA PMPRISC-V Privileged Architecture - Physical Memory ProtectionRISC-V Privileged Architecture - Smepmp Physical Memory Protection Rules

What To Check First When Reading This CSR

  • - pmpcfg0 contains entries 0-3 on RV32 and entries 0-7 in the same CSR on RV64.
  • - PMP is optional; implementations may provide 0, 16, or 64 entries, and every PMP CSR field is WARL and may be read-only zero.
  • - PMP CSRs are accessible only to M-mode.

Risk Checks Before Writing

  • - R/W/X form one collective WARL field. In base PMP (mseccfg.MML=0), combinations with R=0 and W=1 are reserved; Smepmp collectively reinterprets L/R/W/X when MML=1.
  • - L=1 locks pmpNcfg and pmpaddrN until hart reset; with A=TOR it also locks the preceding pmpaddr. Smepmp mseccfg.RLB can bypass locking rules.
  • - Read back WARL fields after writing; do not assume an unimplemented permission or matching mode is accepted.

Put It Back Into A Real Flow

1

Choose OFF, TOR, NA4, or NAPOT in A and encode the range in pmpaddrN (and the preceding address register for TOR).

2

Interpret and write the collective WARL L/R/W/X encoding according to the current mseccfg.MML state.

3

Read back pmpcfg and pmpaddr to confirm the implemented WARL values; set L only after finalizing the configuration.

FAQ

Does pmpcfg0 contain the same number of entries on RV32 and RV64?

No. RV32 pmpcfg0 packs pmp0cfg-pmp3cfg, while RV64 pmpcfg0 packs pmp0cfg-pmp7cfg.