RISC-V pmpcfg0 CSR Register

PMP entry 0 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr0 may still be locked by a later locked TOR entry.

PMP entry 0 is locked; writes to pmp0cfg and pmpaddr0 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. For entry 0, the TOR lower bound is zero, so locking does not involve an earlier pmpaddr.

PMP entry 0 is disabled and matches no addresses.

PMP entry 0 uses top-of-range matching; the upper bound comes from pmpaddr0, and the lower bound is zero.

PMP entry 0 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 0 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr0.

PMP entry 0 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 0 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 0 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 0 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 0 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 0 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 1 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr1 may still be locked by a later locked TOR entry.

PMP entry 1 is locked; writes to pmp1cfg and pmpaddr1 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr0 is also locked.

PMP entry 1 is disabled and matches no addresses.

PMP entry 1 uses top-of-range matching; the upper bound comes from pmpaddr1, and the lower bound comes from pmpaddr0.

PMP entry 1 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 1 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr1.

PMP entry 1 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 1 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 1 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 1 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 1 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 1 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 2 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr2 may still be locked by a later locked TOR entry.

PMP entry 2 is locked; writes to pmp2cfg and pmpaddr2 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr1 is also locked.

PMP entry 2 is disabled and matches no addresses.

PMP entry 2 uses top-of-range matching; the upper bound comes from pmpaddr2, and the lower bound comes from pmpaddr1.

PMP entry 2 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 2 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr2.

PMP entry 2 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 2 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 2 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 2 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 2 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 2 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 3 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr3 may still be locked by a later locked TOR entry.

PMP entry 3 is locked; writes to pmp3cfg and pmpaddr3 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr2 is also locked.

PMP entry 3 is disabled and matches no addresses.

PMP entry 3 uses top-of-range matching; the upper bound comes from pmpaddr3, and the lower bound comes from pmpaddr2.

PMP entry 3 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 3 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr3.

PMP entry 3 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 3 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 3 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 3 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 3 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 3 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 4 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr4 may still be locked by a later locked TOR entry.

PMP entry 4 is locked; writes to pmp4cfg and pmpaddr4 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr3 is also locked.

PMP entry 4 is disabled and matches no addresses.

PMP entry 4 uses top-of-range matching; the upper bound comes from pmpaddr4, and the lower bound comes from pmpaddr3.

PMP entry 4 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 4 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr4.

PMP entry 4 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 4 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 4 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 4 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 4 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 4 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 5 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr5 may still be locked by a later locked TOR entry.

PMP entry 5 is locked; writes to pmp5cfg and pmpaddr5 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr4 is also locked.

PMP entry 5 is disabled and matches no addresses.

PMP entry 5 uses top-of-range matching; the upper bound comes from pmpaddr5, and the lower bound comes from pmpaddr4.

PMP entry 5 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 5 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr5.

PMP entry 5 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 5 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 5 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 5 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 5 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 5 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 6 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr6 may still be locked by a later locked TOR entry.

PMP entry 6 is locked; writes to pmp6cfg and pmpaddr6 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr5 is also locked.

PMP entry 6 is disabled and matches no addresses.

PMP entry 6 uses top-of-range matching; the upper bound comes from pmpaddr6, and the lower bound comes from pmpaddr5.

PMP entry 6 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 6 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr6.

PMP entry 6 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 6 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 6 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 6 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 6 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 6 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 7 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr7 may still be locked by a later locked TOR entry.

PMP entry 7 is locked; writes to pmp7cfg and pmpaddr7 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr6 is also locked.

PMP entry 7 is disabled and matches no addresses.

PMP entry 7 uses top-of-range matching; the upper bound comes from pmpaddr7, and the lower bound comes from pmpaddr6.

PMP entry 7 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 7 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr7.

PMP entry 7 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 7 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 7 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 7 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 7 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 7 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.