RVOPcode
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CSR Bit Fields

RISC-V pmpaddr0 CSR Register

Address 0x3B0Privilege MachineAccess RW / MXLEN: RV32 encodes PA[33:2]; RV64 [53:0] encodes PA[55:2] and [63:54] is zeroMachine physical memory protection CSRs

pmpaddr0 (0x3B0) is the WARL address register for machine PMP entry 0; it encodes physical address bits 33:2 on RV32 and 55:2 on RV64.

Related Search Terms
pmpaddr0 CSRpmpaddr0 0x3B0pmpaddr0 TORpmpaddr0 NAPOTpmpaddr0 grainpmp0cfg A
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
063:54WARL/reads zeroaddress[55:2]53:0WARL/may be RO0
Field Map

Understand pmpaddr0 By Bit Fields

2 key fields
63:54

0

WARL/reads zero

RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

0 (bits 63:54) — RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

What This Field Controls

  • - RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
53:0

address[55:2]

WARL/may be RO0

RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

address[55:2] (bits 53:0) — RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

What This Field Controls

  • - RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

pmpaddr0 is the MXLEN-bit WARL address encoding for PMP entry 0. pmp0cfg.A determines its meaning; TOR uniquely uses a fixed lower bound of zero.

RV32 pmpaddr encodes PA[33:2]; RV64 [53:0] encodes PA[55:2], with [63:54] zero.
TOR entry 0 uses zero as its lower bound; NAPOT uses low pmpaddr0 bits to encode a naturally aligned power-of-two region of at least 8 bytes.
Platform grain changes low-bit readback; pmp0cfg.L or a locked TOR entry 1 can cause pmpaddr0 writes to be ignored.
RISC-V ISA Manual 2026-07-09 release - Machine ISA PMPRISC-V Privileged Architecture - Physical Memory ProtectionRISC-V Privileged Architecture - Smepmp Physical Memory Protection Rules

What To Check First When Reading This CSR

  • - PMP is optional; implementations may provide 0, 16, or 64 entries, with the lowest-numbered entries implemented first. Every PMP CSR field is WARL and may be read-only zero.
  • - pmpaddr0 is accessible only to M-mode. Its readback depends on pmp0cfg.A and the platform-wide PMP grain G.
  • - With G>=2 and A=NAPOT, pmpaddr0[G-2:0] reads as ones; with G>=1 and A=OFF/TOR, pmpaddr0[G-1:0] reads as zeros, but those bits do not affect TOR matching. Changing A changes readback, not the underlying stored value.
  • - Reset specifies defaults only for writable PMP A/L fields (subject to platform overrides); pmpaddr0's reset value is unspecified, but no WARL field contains an illegal value.

Risk Checks Before Writing

  • - Writes to pmpaddr0 are ignored until hart reset when pmp0cfg.L=1; pmpaddr0 is also unwritable as entry 1's lower bound when entry 1 is locked with pmp1cfg.A=TOR. Smepmp mseccfg.RLB can bypass locking rules.
  • - pmpaddr0 is WARL; read it back after writing and interpret the masked value using the current pmp0cfg.A and grain.
  • - With pmp0cfg.A=TOR, entry 0 matches 0 <= y < pmpaddr0; a zero pmpaddr0 gives an empty range. NA4 is not selectable when G>=1.

Put It Back Into A Real Flow

1

Read pmp0cfg.A to determine whether entry 0 uses OFF, TOR, NA4, or NAPOT.

2

Write pmpaddr0 for the selected mode; TOR has a fixed zero lower bound, while NAPOT encodes range size in low bits.

3

Read back pmpaddr0 and pmp0cfg to confirm the effective WARL/grain encoding; set pmp0cfg.L only after final verification.

FAQ

Where does pmpaddr0's TOR lower bound come from?

PMP entry 0 is the special case: with pmp0cfg.A=TOR, its lower bound is zero and pmpaddr0 supplies the upper bound; an upper bound of zero matches no addresses.

Why can pmpaddr0 read back differently from the written value?

pmpaddr0 is WARL, and platform grain plus pmp0cfg.A masks low-bit readback: NAPOT can read ones while OFF/TOR reads zeros. Mode changes do not alter the underlying stored value.