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CSR Bit Fields

RISC-V menvcfg CSR Register

Address 0x30APrivilege MachineAccess RW / XLENMachine delegation, environment-configuration, and state-enable CSRs

Machine environment configuration register; controls execution-environment features in machine mode.

Related Search Terms
menvcfg CSRmenvcfg 0x30Amachine environment configmenvcfg STCE PBMTEmenvcfg FIOM CBZERISC-V menvcfg
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
STCE63RWFIOM0RW
Field Map

Understand menvcfg By Bit Fields

7 key fields
63

STCE

RW

Access control for stimecmp related to the Sstc extension.

STCE (bit 63) — Access control for stimecmp related to the Sstc extension.

What This Field Controls

  • - Access control for stimecmp related to the Sstc extension.

Common Values

0Disabled

Lower privilege levels cannot directly use the Sstc stimecmp access path.

1Enabled

Allows lower privilege levels to use the Sstc-defined stimecmp access path.

62

PBMTE

RW

Enable for the Svpbmt page-based memory types extension.

PBMTE (bit 62) — Enable for the Svpbmt page-based memory types extension.

What This Field Controls

  • - Enable for the Svpbmt page-based memory types extension.

Common Values

0Disabled

PBMT use in lower-privilege page-table entries is not enabled.

1Enabled

Enables PBMT use in lower-privilege page-table entries.

61

ADUE

RW

Controls hardware updates of page-table A/D bits.

ADUE (bit 61) — Controls hardware updates of page-table A/D bits.

What This Field Controls

  • - Controls hardware updates of page-table A/D bits.

Common Values

0Disabled

Hardware A/D-bit updating is not enabled by this field; page-table A/D behavior follows the relevant extension rules.

1Enabled

Enables the hardware path for updating page-table A/D bits.

7

CBZE

RW

Allows lower privilege use of cache-block zero behavior.

CBZE (bit 7) — Allows lower privilege use of cache-block zero behavior.

What This Field Controls

  • - Allows lower privilege use of cache-block zero behavior.

Common Values

0Disabled

Lower-privilege CBO.ZERO is unavailable or traps.

1Enabled

Allows lower privilege levels to execute CBO.ZERO.

6

CBCFE

RW

Cache-block clean/flush instruction enable.

CBCFE (bit 6) — Cache-block clean/flush instruction enable.

What This Field Controls

  • - Cache-block clean/flush instruction enable.

Common Values

0Disabled

Lower-privilege CBO.CLEAN/CBO.FLUSH are unavailable or trap.

1Enabled

Allows lower privilege levels to execute CBO.CLEAN/CBO.FLUSH.

5:4

CBIE

RW-R

Cache-block invalidate instruction enable; encoding selects trap, execute as flush, reserved, or execute as invalidate.

CBIE (bits 5:4) — Cache-block invalidate instruction enable; encoding selects trap, execute as flush, reserved, or execute as invalidate.

What This Field Controls

  • - Cache-block invalidate instruction enable; encoding selects trap, execute as flush, reserved, or execute as invalidate.

Common Values

0Illegal instruction

Lower-privilege CBO.INVAL instructions raise an illegal-instruction exception.

1Flush behavior

Lower-privilege CBO.INVAL executes with CBO.FLUSH behavior.

2Reserved

Reserved encoding; portable software must not write or depend on it.

3Invalidate behavior

Lower-privilege CBO.INVAL executes with invalidate behavior.

0

FIOM

RW

Makes FENCE I/O ordering imply memory ordering.

FIOM (bit 0) — Makes FENCE I/O ordering imply memory ordering.

What This Field Controls

  • - Makes FENCE I/O ordering imply memory ordering.

Common Values

0Disabled

FENCE ordering of I/O does not imply ordering of main memory.

1Enabled

FENCE ordering of I/O also implies ordering of main memory.

Official Basis & Search Notes

menvcfg is a RW CSR in machine delegation, environment-configuration, and state-enable csrs at 0x30A. Check privilege and implemented extensions before interpreting its bit fields.

menvcfg address, lowest access privilege, and access class are checked against the official CSR table: 0x30A, Machine, RW.
Read it as part of machine delegation, environment-configuration, and state-enable csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements menvcfg; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x30A and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads menvcfg to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can menvcfg be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records menvcfg as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing menvcfg?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.