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CSR Bit Fields

RISC-V menvcfg CSR Register

Address 0x30APrivilege MachineAccess RW / 64-bit; RV32 accesses the low/high halves through menvcfg and menvcfghMachine delegation, environment-configuration, and state-enable CSRs

Machine environment configuration register; controls execution-environment characteristics for modes less privileged than M.

Related Search Terms
menvcfg CSRmenvcfg 0x30Amenvcfg STCE PBMTE ADUEmenvcfg CBIE PMMmenvcfg FIOMRISC-V menvcfg
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
STCE63RW/RO0FIOM0RW/RO0
Field Map

Understand menvcfg By Bit Fields

13 key fields
63

STCE

RW/RO0

Sstc STimecmp Enable. When implemented and set, enables stimecmp for S-mode; otherwise access below M-mode raises illegal-instruction. RO0 if Sstc is not implemented.

STCE (bit 63) — Sstc STimecmp Enable. When implemented and set, enables stimecmp for S-mode; otherwise access below M-mode raises illegal-instruction. RO0 if Sstc is not implemented.

What This Field Controls

  • - Sstc STimecmp Enable. When implemented and set, enables stimecmp for S-mode; otherwise access below M-mode raises illegal-instruction. RO0 if Sstc is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

62

PBMTE

RW/RO0

Controls whether Svpbmt is available for S-mode and G-stage address translation; RO0 if Svpbmt is not implemented.

PBMTE (bit 62) — Controls whether Svpbmt is available for S-mode and G-stage address translation; RO0 if Svpbmt is not implemented.

What This Field Controls

  • - Controls whether Svpbmt is available for S-mode and G-stage address translation; RO0 if Svpbmt is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

61

ADUE

RW/RO0

When Svadu is implemented, controls hardware updating of PTE A/D bits for S-mode and G-stage translations; RO0 if Svadu is not implemented.

ADUE (bit 61) — When Svadu is implemented, controls hardware updating of PTE A/D bits for S-mode and G-stage translations; RO0 if Svadu is not implemented.

What This Field Controls

  • - When Svadu is implemented, controls hardware updating of PTE A/D bits for S-mode and G-stage translations; RO0 if Svadu is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

60

CDE

RW/RO0

Smcdeleg Counter Delegation Enable. When set, enables Smcdeleg counter delegation; RO0 if Smcdeleg is not implemented.

CDE (bit 60) — Smcdeleg Counter Delegation Enable. When set, enables Smcdeleg counter delegation; RO0 if Smcdeleg is not implemented.

What This Field Controls

  • - Smcdeleg Counter Delegation Enable. When set, enables Smcdeleg counter delegation; RO0 if Smcdeleg is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

59

DTE

RW/RO0

Ssdbltrp double-trap-enable field. When zero, the implementation behaves as though Ssdbltrp is not implemented; it is RO0 when Ssdbltrp is not implemented.

DTE (bit 59) — Ssdbltrp double-trap-enable field. When zero, the implementation behaves as though Ssdbltrp is not implemented; it is RO0 when Ssdbltrp is not implemented.

What This Field Controls

  • - Ssdbltrp double-trap-enable field. When zero, the implementation behaves as though Ssdbltrp is not implemented; it is RO0 when Ssdbltrp is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

34:32

PMM

WARL/RO0

Smnpm pointer masking field for the next-lower privilege mode. Legal values: 00 disabled, 01 reserved, 10 PMLEN=XLEN-57, 11 PMLEN=XLEN-48; RO0 if Smnpm is not implemented and RO0 on RV32.

PMM (bits 34:32) — Smnpm pointer masking field for the next-lower privilege mode. Legal values: 00 disabled, 01 reserved, 10 PMLEN=XLEN-57, 11 PMLEN=XLEN-48; RO0 if Smnpm is not implemented and RO0 on RV32.

What This Field Controls

  • - Smnpm pointer masking field for the next-lower privilege mode. Legal values: 00 disabled, 01 reserved, 10 PMLEN=XLEN-57, 11 PMLEN=XLEN-48; RO0 if Smnpm is not implemented and RO0 on RV32.

Common Values

00Disabled

Pointer masking disabled, PMLEN=0.

01Reserved

Reserved encoding; portable software should not write it.

10PMLEN=XLEN-57

Pointer masking enabled; on RV64 PMLEN=7.

11PMLEN=XLEN-48

Pointer masking enabled; on RV64 PMLEN=16.

7

CBZE

RW/RO0

Zicboz Cache Block Zero instruction enable for modes less privileged than M; RO0 if Zicboz is not implemented.

CBZE (bit 7) — Zicboz Cache Block Zero instruction enable for modes less privileged than M; RO0 if Zicboz is not implemented.

What This Field Controls

  • - Zicboz Cache Block Zero instruction enable for modes less privileged than M; RO0 if Zicboz is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

6

CBCFE

RW/RO0

Zicbom Cache Block Clean and Flush instruction enable for modes less privileged than M; RO0 if Zicbom is not implemented.

CBCFE (bit 6) — Zicbom Cache Block Clean and Flush instruction enable for modes less privileged than M; RO0 if Zicbom is not implemented.

What This Field Controls

  • - Zicbom Cache Block Clean and Flush instruction enable for modes less privileged than M; RO0 if Zicbom is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

5:4

CBIE

WARL/RO0

Zicbom Cache Block Invalidate instruction enable WARL field: 00 traps, 01 executes as flush, 10 reserved, 11 executes as invalidate unless lower mode configures flush; RO0 if Zicbom is not implemented.

CBIE (bits 5:4) — Zicbom Cache Block Invalidate instruction enable WARL field: 00 traps, 01 executes as flush, 10 reserved, 11 executes as invalidate unless lower mode configures flush; RO0 if Zicbom is not implemented.

What This Field Controls

  • - Zicbom Cache Block Invalidate instruction enable WARL field: 00 traps, 01 executes as flush, 10 reserved, 11 executes as invalidate unless lower mode configures flush; RO0 if Zicbom is not implemented.

Common Values

00Illegal-instruction exception

CBO.INVAL executed below M-mode raises an illegal-instruction exception.

01Execute as flush

CBO.INVAL executes and performs a flush operation.

10Reserved

Reserved encoding; portable software should not write it.

11Execute as invalidate

CBO.INVAL executes and performs an invalidate operation unless configured by a mode below M to perform flush.

3

SSE

RW/RO0

Zicfiss shadow stack enable. When set, activates Zicfiss in S-mode; when clear, Zicfiss behavior below M follows the specified disabled rules; RO0 if Zicfiss is not implemented.

SSE (bit 3) — Zicfiss shadow stack enable. When set, activates Zicfiss in S-mode; when clear, Zicfiss behavior below M follows the specified disabled rules; RO0 if Zicfiss is not implemented.

What This Field Controls

  • - Zicfiss shadow stack enable. When set, activates Zicfiss in S-mode; when clear, Zicfiss behavior below M follows the specified disabled rules; RO0 if Zicfiss is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

2

LPE

RW/RO0

Zicfilp landing-pad enable for S-mode, or U-mode when S-mode is not implemented; RO0 if Zicfilp is not implemented.

LPE (bit 2) — Zicfilp landing-pad enable for S-mode, or U-mode when S-mode is not implemented; RO0 if Zicfilp is not implemented.

What This Field Controls

  • - Zicfilp landing-pad enable for S-mode, or U-mode when S-mode is not implemented; RO0 if Zicfilp is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

0

FIOM

RW/RO0

Fence of I/O implies Memory. When set, FENCE I/O ordering and ordered I/O atomics below M also imply main-memory ordering. May be RO0 if S-mode is absent or satp.MODE is always Bare.

FIOM (bit 0) — Fence of I/O implies Memory. When set, FENCE I/O ordering and ordered I/O atomics below M also imply main-memory ordering. May be RO0 if S-mode is absent or satp.MODE is always Bare.

What This Field Controls

  • - Fence of I/O implies Memory. When set, FENCE I/O ordering and ordered I/O atomics below M also imply main-memory ordering. May be RO0 if S-mode is absent or satp.MODE is always Bare.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

58:35, 31:8, 1

WPRI

WPRI

Reserved/WPRI fields in the menvcfg layout; software should preserve them when writing other fields and ignore them on reads.

WPRI (bits 58:35, 31:8, 1) — Reserved/WPRI fields in the menvcfg layout; software should preserve them when writing other fields and ignore them on reads.

What This Field Controls

  • - Reserved/WPRI fields in the menvcfg layout; software should preserve them when writing other fields and ignore them on reads.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

menvcfg is the 64-bit CSR through which M-mode controls selected execution-environment features for lower privilege modes. Most bits are writable only when their defining extension is implemented; otherwise they read as zero.

RV32 uses menvcfgh to access the upper 32 bits of menvcfg.
PBMTE and ADUE changes require the specified SFENCE.VMA synchronization.
CBIE and PMM are WARL fields and each has reserved encodings.
RISC-V Privileged Architecture Manual v20260120, CSR tableRISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

  • - menvcfg is a 64-bit read/write CSR and should not exist if U-mode is not supported.
  • - On RV32, menvcfgh aliases bits 63:32 of menvcfg; menvcfgh does not exist on RV64.
  • - Many fields are present only with their defining extensions and are read-only zero when the extension is not implemented.

Risk Checks Before Writing

  • - After changing PBMTE or ADUE, execute SFENCE.VMA with rs1=x0 and rs2=x0 to synchronize address-translation caches as specified.
  • - Do not write reserved CBIE=10 or PMM=01 values in portable software.
  • - Preserve WPRI fields and read back WARL fields such as PMM and CBIE to confirm accepted values.

Put It Back Into A Real Flow

1

Check whether the field-defining extension is implemented before relying on a menvcfg bit.

2

Set only the specific lower-privilege environment controls needed by the OS or hypervisor.

3

Read back WARL/RO0 fields and perform required fences after address-translation-affecting changes.

FAQ

Can menvcfg be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records menvcfg as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing menvcfg?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.