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CSR Bit Fields

RISC-V menvcfgh CSR Register

Address 0x31APrivilege MachineAccess RW / RV32-only high half / 32-bitMachine delegation, environment-configuration, and state-enable CSRs

menvcfgh (0x31A) is the RV32 M-mode high-half CSR for bits 63:32 of menvcfg.

Related Search Terms
menvcfgh CSRmenvcfgh 0x31ARV32 menvcfg highmenvcfgh STCEmenvcfgh PBMTE ADUEmenvcfgh PMM
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand menvcfgh By Bit Fields

0 key fields
Official Basis & Search Notes

menvcfgh exists only on RV32 as the access window for menvcfg bits 63:32. It contains STCE, PBMTE, ADUE, CDE, DTE, PMM, and WPRI high fields; whether those fields are writable depends on the corresponding extensions.

menvcfgh is the RV32 high-half alias of menvcfg; RV64 uses 64-bit menvcfg and has no menvcfgh CSR.
After PBMTE or ADUE changes, the official manual requires SFENCE.VMA with rs1=x0 and rs2=x0 to synchronize address-translation caches.
PMM maps menvcfg bits 33:32 but is read-only zero on RV32.
RISC-V Privileged Architecture Manual v20260120, CSR tableRISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

  • - Only RV32 uses menvcfgh to access bits 63:32 of menvcfg; this high-half CSR does not exist on RV64.
  • - Use address 0x31A and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not infer undefined functions from bit positions when reading WARL, RO0, or WPRI fields; interpret them through the matching full CSR and extension rules.

Risk Checks Before Writing

  • - Preserve WPRI bits and unchanged fields when writing; whether each writable bit is actually writable depends on the corresponding extension and implementation.
  • - Read back WARL fields after writes to confirm the value accepted by the implementation.

Put It Back Into A Real Flow

1

On RV32, read menvcfgh before initializing lower-privilege environment state to observe the upper 32 bits of menvcfg.

2

Modify only target fields and preserve all other bits.

3

When needed, read the CSR back and confirm the effect through later lower-privilege accesses, traps, or state updates.

FAQ

Does menvcfgh exist on RV64?

No. The official CSR table defines menvcfgh as the RV32 CSR for accessing the upper 32 bits of menvcfg.

Is every menvcfgh bit necessarily writable?

No. Several fields are read-only zero when their corresponding extension is absent, and WPRI bits should be preserved when writing other fields.