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CSR Bit Fields

RISC-V senvcfg CSR Register

Address 0x10APrivilege SupervisorAccess RW / XLENSupervisor environment-configuration and state-enable CSRs

Supervisor environment configuration register controlling FIOM, CBO, pointer masking, Zicfilp, and Zicfiss switches for the U-mode execution environment.

Related Search Terms
senvcfg CSRsenvcfg 0x10Asenvcfg FIOMsenvcfg CBIE CBCFE CBZEsenvcfg PMMsenvcfg LPE SSE
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
WPRI63:34WPRI/RV64FIOM0RW/may be RO0
Field Map

Understand senvcfg By Bit Fields

10 key fields
63:34

WPRI

WPRI/RV64

High reserved writes-preserve-values field in RV64 `senvcfg`; these bits are not present in the RV32 format.

WPRI (bits 63:34) — High reserved writes-preserve-values field in RV64 `senvcfg`; these bits are not present in the RV32 format.

What This Field Controls

  • - High reserved writes-preserve-values field in RV64 `senvcfg`; these bits are not present in the RV32 format.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

33:32

PMM

WARL/RO0 on RV32

Ssnpm-defined pointer-masking mode field for U/VU mode. The field is read-only zero when Ssnpm is not implemented and on RV32.

PMM (bits 33:32) — Ssnpm-defined pointer-masking mode field for U/VU mode. The field is read-only zero when Ssnpm is not implemented and on RV32.

What This Field Controls

  • - Ssnpm-defined pointer-masking mode field for U/VU mode. The field is read-only zero when Ssnpm is not implemented and on RV32.

Common Values

00Disabled

Pointer masking is disabled, PMLEN=0.

01Reserved

Reserved encoding; software must not write or depend on it.

10PMLEN=XLEN-57

Pointer masking is enabled; PMLEN=7 on RV64.

11PMLEN=XLEN-48

Pointer masking is enabled; PMLEN=16 on RV64.

31:8

WPRI

WPRI

Reserved writes-preserve-values field.

WPRI (bits 31:8) — Reserved writes-preserve-values field.

What This Field Controls

  • - Reserved writes-preserve-values field.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

7

CBZE

RW/may be RO0

Zicboz-defined CBO.ZERO enable. U/VU-mode execution of CBO.ZERO is allowed only when it is also enabled for S-mode and CBZE=1; without Zicboz this bit is read-only zero.

CBZE (bit 7) — Zicboz-defined CBO.ZERO enable. U/VU-mode execution of CBO.ZERO is allowed only when it is also enabled for S-mode and CBZE=1; without Zicboz this bit is read-only zero.

What This Field Controls

  • - Zicboz-defined CBO.ZERO enable. U/VU-mode execution of CBO.ZERO is allowed only when it is also enabled for S-mode and CBZE=1; without Zicboz this bit is read-only zero.

Common Values

0Disabled

U/VU-mode CBO.ZERO raises an illegal-instruction exception, or the bit is read-only zero without Zicboz.

1Enabled

Allows U/VU-mode CBO.ZERO when CBO.ZERO is also enabled for S-mode.

6

CBCFE

RW/may be RO0

Zicbom-defined CBO.CLEAN/CBO.FLUSH enable. U/VU-mode execution is allowed only when these instructions are also enabled for S-mode and CBCFE=1; without Zicbom this bit is read-only zero.

CBCFE (bit 6) — Zicbom-defined CBO.CLEAN/CBO.FLUSH enable. U/VU-mode execution is allowed only when these instructions are also enabled for S-mode and CBCFE=1; without Zicbom this bit is read-only zero.

What This Field Controls

  • - Zicbom-defined CBO.CLEAN/CBO.FLUSH enable. U/VU-mode execution is allowed only when these instructions are also enabled for S-mode and CBCFE=1; without Zicbom this bit is read-only zero.

Common Values

0Disabled

U/VU-mode CBO.CLEAN/CBO.FLUSH raise illegal-instruction exceptions, or the bit is read-only zero without Zicbom.

1Enabled

Allows U/VU-mode CBO.CLEAN/CBO.FLUSH when they are also enabled for S-mode.

5:4

CBIE

WARL/may be RO0

Zicbom-defined WARL field controlling CBO.INVAL; `10b` is reserved. Without Zicbom this field is read-only zero.

CBIE (bits 5:4) — Zicbom-defined WARL field controlling CBO.INVAL; `10b` is reserved. Without Zicbom this field is read-only zero.

What This Field Controls

  • - Zicbom-defined WARL field controlling CBO.INVAL; `10b` is reserved. Without Zicbom this field is read-only zero.

Common Values

00Illegal instruction

U/VU-mode CBO.INVAL raises an illegal-instruction exception.

01Flush behavior

If also enabled for S-mode, U/VU-mode CBO.INVAL executes with CBO.FLUSH behavior.

10Reserved

Reserved encoding; software must not write or depend on it.

11Invalidate behavior

If also enabled for S-mode and S-mode does not force flush behavior, U/VU-mode CBO.INVAL executes with invalidate behavior.

3

SSE

RW/may be RO0

Zicfiss-defined shadow stack enable. SSE=1 activates Zicfiss in U/VU mode; SSE=0 leaves Zicfiss inactive in U/VU mode. Without Zicfiss this bit is read-only zero.

SSE (bit 3) — Zicfiss-defined shadow stack enable. SSE=1 activates Zicfiss in U/VU mode; SSE=0 leaves Zicfiss inactive in U/VU mode. Without Zicfiss this bit is read-only zero.

What This Field Controls

  • - Zicfiss-defined shadow stack enable. SSE=1 activates Zicfiss in U/VU mode; SSE=0 leaves Zicfiss inactive in U/VU mode. Without Zicfiss this bit is read-only zero.

Common Values

0Disabled

Zicfiss remains inactive in U/VU mode; without Zicfiss the bit is read-only zero.

1Enabled

Activates Zicfiss in U/VU mode.

2

LPE

RW/may be RO0

Zicfilp-defined landing-pad enable. LPE=1 enables Zicfilp in U/VU mode; LPE=0 leaves Zicfilp disabled in U/VU mode. Without Zicfilp this bit is read-only zero.

LPE (bit 2) — Zicfilp-defined landing-pad enable. LPE=1 enables Zicfilp in U/VU mode; LPE=0 leaves Zicfilp disabled in U/VU mode. Without Zicfilp this bit is read-only zero.

What This Field Controls

  • - Zicfilp-defined landing-pad enable. LPE=1 enables Zicfilp in U/VU mode; LPE=0 leaves Zicfilp disabled in U/VU mode. Without Zicfilp this bit is read-only zero.

Common Values

0Disabled

Zicfilp is not enabled in U/VU mode; without Zicfilp the bit is read-only zero.

1Enabled

Enables Zicfilp in U/VU mode.

1

WPRI

WPRI

Reserved writes-preserve-values field.

WPRI (bit 1) — Reserved writes-preserve-values field.

What This Field Controls

  • - Reserved writes-preserve-values field.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

0

FIOM

RW/may be RO0

Fence of I/O implies Memory. When FIOM=1, U-mode FENCE ordering of device I/O also implies ordering of main memory; an implementation may make FIOM read-only zero when `satp.MODE` is read-only Bare.

FIOM (bit 0) — Fence of I/O implies Memory. When FIOM=1, U-mode FENCE ordering of device I/O also implies ordering of main memory; an implementation may make FIOM read-only zero when `satp.MODE` is read-only Bare.

What This Field Controls

  • - Fence of I/O implies Memory. When FIOM=1, U-mode FENCE ordering of device I/O also implies ordering of main memory; an implementation may make FIOM read-only zero when `satp.MODE` is read-only Bare.

Common Values

0Disabled

U-mode FENCE I/O ordering does not imply main-memory ordering.

1Enabled

U-mode I/O FENCE ordering also includes main-memory ordering.

Official Basis & Search Notes

senvcfg controls the U/VU-mode execution environment. The current official format includes FIOM, LPE, SSE, CBIE, CBCFE, CBZE, and RV64 PMM, with read-only-zero behavior for absent extensions.

The official Supervisor-Level ISA defines `senvcfg` as an SXLEN-bit read/write CSR.
CBO fields allow U/VU-mode execution only when the corresponding Zicboz/Zicbom extension exists and the instruction is also enabled for S-mode.
PMM is an RV64 WARL field from Ssnpm; it is read-only zero without Ssnpm and on RV32.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Supervisor-Level ISA

What To Check First When Reading This CSR

  • - `senvcfg` is an SXLEN-bit read/write CSR; the RV64 format includes PMM[33:32], while PMM is read-only zero on RV32.
  • - FIOM, CBO, PMM, LPE, and SSE fields all have extension or mode conditions; corresponding fields may be read-only zero when the related extension is absent.

Risk Checks Before Writing

  • - Preserve WPRI bits and do not write reserved encodings such as PMM=01 or CBIE=10.
  • - Before enabling CBO fields, also confirm the same instruction is enabled for S-mode.

Put It Back Into A Real Flow

1

Confirm the target hart extensions: Zicboz, Zicbom, Ssnpm, Zicfilp, Zicfiss, and `satp` mode capability.

2

Modify only the needed senvcfg fields and preserve WPRI bits.

3

Read back to confirm the actual accepted values of WARL/read-only-zero fields.

FAQ

Can senvcfg be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records senvcfg as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing senvcfg?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.