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CSR Bit Fields

RISC-V senvcfg CSR Register

Address 0x10APrivilege SupervisorAccess RW / XLENSupervisor environment-configuration and state-enable CSRs

Supervisor environment configuration register; controls execution-environment features in S-mode.

Related Search Terms
senvcfg CSRsenvcfg 0x10Asupervisor environment configsenvcfg FIOMsenvcfg CBZE CBCFERISC-V senvcfg
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:8FIOM0RW
Field Map

Understand senvcfg By Bit Fields

4 key fields
7

CBZE

RW

Allows lower privilege use of cache-block zero behavior.

CBZE (bit 7) — Allows lower privilege use of cache-block zero behavior.

What This Field Controls

  • - Allows lower privilege use of cache-block zero behavior.

Common Values

0Disabled

U/VU-mode CBO.ZERO is unavailable or traps.

1Enabled

Allows U/VU-mode execution of CBO.ZERO.

6

CBCFE

RW

Cache-block clean/flush instruction enable.

CBCFE (bit 6) — Cache-block clean/flush instruction enable.

What This Field Controls

  • - Cache-block clean/flush instruction enable.

Common Values

0Disabled

U/VU-mode CBO.CLEAN/CBO.FLUSH are unavailable or trap.

1Enabled

Allows U/VU-mode execution of CBO.CLEAN/CBO.FLUSH.

5:4

CBIE

RW-R

Cache-block invalidate instruction enable; encoding selects trap, execute as flush, reserved, or execute as invalidate.

CBIE (bits 5:4) — Cache-block invalidate instruction enable; encoding selects trap, execute as flush, reserved, or execute as invalidate.

What This Field Controls

  • - Cache-block invalidate instruction enable; encoding selects trap, execute as flush, reserved, or execute as invalidate.

Common Values

0Illegal instruction

Lower-privilege CBO.INVAL instructions raise an illegal-instruction exception.

1Flush behavior

Lower-privilege CBO.INVAL executes with CBO.FLUSH behavior.

2Reserved

Reserved encoding; portable software must not write or depend on it.

3Invalidate behavior

Lower-privilege CBO.INVAL executes with invalidate behavior.

0

FIOM

RW

Makes FENCE I/O ordering imply memory ordering.

FIOM (bit 0) — Makes FENCE I/O ordering imply memory ordering.

What This Field Controls

  • - Makes FENCE I/O ordering imply memory ordering.

Common Values

0Disabled

FENCE ordering of I/O does not imply ordering of main memory.

1Enabled

FENCE ordering of I/O also implies ordering of main memory.

Official Basis & Search Notes

senvcfg is a RW CSR in supervisor environment-configuration and state-enable csrs at 0x10A. Check privilege and implemented extensions before interpreting its bit fields.

senvcfg address, lowest access privilege, and access class are checked against the official CSR table: 0x10A, Supervisor, RW.
Read it as part of supervisor environment-configuration and state-enable csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements senvcfg; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x10A and the lowest access privilege (Supervisor) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads senvcfg to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can senvcfg be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records senvcfg as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing senvcfg?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.