RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V henvcfg CSR Register

Address 0x60APrivilege HypervisorAccess HRW / HSXLENHypervisor and virtualization CSRs

henvcfg is a Hypervisor environment-configuration CSR.

Related Search Terms
henvcfg CSRhenvcfg 0x60Aguest execution environment configuration bitsHypervisor
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
STCE63RWFIOM0RW
Field Map

Understand henvcfg By Bit Fields

7 key fields
63

STCE

RW

Sstc enable bit for the VS-mode vstimecmp access path.

STCE (bit 63) — Sstc enable bit for the VS-mode vstimecmp access path.

What This Field Controls

  • - Sstc enable bit for the VS-mode vstimecmp access path.

Common Values

0Disabled

VS-mode access to stimecmp, actually vstimecmp, raises a virtual-instruction exception.

1Enabled

Allows VS-mode to access the Sstc-defined vstimecmp.

↗Open Official Manual
62

PBMTE

RW

Controls whether Svpbmt is available for VS-stage address translation.

PBMTE (bit 62) — Controls whether Svpbmt is available for VS-stage address translation.

What This Field Controls

  • - Controls whether Svpbmt is available for VS-stage address translation.

Common Values

0Disabled

VS-stage address translation behaves as though Svpbmt were not implemented.

1Enabled

Svpbmt is available for VS-stage address translation.

↗Open Official Manual
61

ADUE

RW

Controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation.

ADUE (bit 61) — Controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation.

What This Field Controls

  • - Controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation.

Common Values

0Disabled

VS-stage address translation behaves as though Svade were implemented, requiring software handling of A/D bits.

1Enabled

Hardware updating of PTE A/D bits is enabled for VS-stage address translation.

↗Open Official Manual
7

CBZE

RW

Controls whether HS-qualified CBO.ZERO may execute in VS/VU.

CBZE (bit 7) — Controls whether HS-qualified CBO.ZERO may execute in VS/VU.

What This Field Controls

  • - Controls whether HS-qualified CBO.ZERO may execute in VS/VU.

Common Values

0Disabled

HS-qualified CBO.ZERO in VS/VU raises a virtual-instruction exception.

1Enabled

Allows HS-qualified CBO.ZERO to execute in VS/VU.

↗Open Official Manual
6

CBCFE

RW

Controls whether HS-qualified CBO.CLEAN/CBO.FLUSH may execute in VS/VU.

CBCFE (bit 6) — Controls whether HS-qualified CBO.CLEAN/CBO.FLUSH may execute in VS/VU.

What This Field Controls

  • - Controls whether HS-qualified CBO.CLEAN/CBO.FLUSH may execute in VS/VU.

Common Values

0Disabled

HS-qualified CBO.CLEAN/CBO.FLUSH in VS/VU raises a virtual-instruction exception.

1Enabled

Allows HS-qualified CBO.CLEAN/CBO.FLUSH to execute in VS/VU.

↗Open Official Manual
5:4

CBIE

RW

Controls availability and behavior of HS-qualified CBO.INVAL in VS/VU.

CBIE (bits 5:4) — Controls availability and behavior of HS-qualified CBO.INVAL in VS/VU.

What This Field Controls

  • - Controls availability and behavior of HS-qualified CBO.INVAL in VS/VU.

Common Values

0Disabled

HS-qualified CBO.INVAL in VS/VU raises a virtual-instruction exception.

1Flush behavior

CBO.INVAL may execute in VS/VU and performs flush behavior.

2Reserved

Reserved encoding; portable software must not write or depend on it.

3Invalidate behavior

CBO.INVAL may execute in VS/VU and performs invalidate behavior unless HS configuration forces flush behavior.

↗Open Official Manual
0

FIOM

RW

Controls whether FENCE I/O ordering also implies memory ordering when V=1.

FIOM (bit 0) — Controls whether FENCE I/O ordering also implies memory ordering when V=1.

What This Field Controls

  • - Controls whether FENCE I/O ordering also implies memory ordering when V=1.

Common Values

0Disabled

When V=1, FENCE ordering of I/O does not imply ordering of main memory.

1Enabled

When V=1, FENCE ordering of I/O also implies ordering of main memory.

↗Open Official Manual
Official Basis & Search Notes

henvcfg is a Hypervisor environment-configuration CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

henvcfg address, access class, and width are checked against the official CSR tables: 0x60A, HRW, HSXLEN.
henvcfg fields are interpreted by the corresponding Hypervisor extension section; unimplemented fields must not be treated as fixed writable bits.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - henvcfg is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - When writing henvcfg, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can henvcfg be accessed through a supervisor CSR alias?

Do not treat henvcfg as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.