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CSR Bit Fields

RISC-V fcsr CSR Register

Address 0x003Privilege UserAccess RW / 32User floating-point state CSRs

Floating-point control and status register; combines frm (rounding mode) and fflags (exception flags).

Related Search Terms
fcsr CSRfcsr 0x003fcsr fflags frmfloating point statusfloating point control CSRRISC-V fcsr
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:8ReservedFRM7:5RWNV4RWFFLAGS4:0RW
Field Map

Understand fcsr By Bit Fields

8 key fields
XLEN-1:8

Reserved

Reserved

Reserved for other standard extensions. If those extensions are absent, writes are ignored and reads return zero; standard software should preserve these bits.

Reserved (bits XLEN-1:8) — Reserved for other standard extensions. If those extensions are absent, writes are ignored and reads return zero; standard software should preserve these bits.

What This Field Controls

  • - Reserved for other standard extensions. If those extensions are absent, writes are ignored and reads return zero; standard software should preserve these bits.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

7:5

FRM

RW

Dynamic rounding mode. 101, 110, and 111 are reserved encodings in frm/fcsr; 111 (DYN) selects frm only in an instruction rm field.

FRM (bits 7:5) — Dynamic rounding mode. 101, 110, and 111 are reserved encodings in frm/fcsr; 111 (DYN) selects frm only in an instruction rm field.

What This Field Controls

  • - Dynamic rounding mode. 101, 110, and 111 are reserved encodings in frm/fcsr; 111 (DYN) selects frm only in an instruction rm field.

Common Values

000RNE

Round to Nearest, ties to Even.

001RTZ

Round towards Zero.

010RDN

Round Down (towards negative infinity).

011RUP

Round Up (towards positive infinity).

100RMM

Round to Nearest, ties to Max Magnitude.

101Reserved

Reserved for future use.

110Reserved

Reserved for future use.

111Reserved

Reserved in frm/fcsr; DYN applies only to an instruction rm field.

4:0

FFLAGS

RW

Alias of fflags: accrued NV, DZ, OF, UF, and NX exception flags.

FFLAGS (bits 4:0) — Alias of fflags: accrued NV, DZ, OF, UF, and NX exception flags.

What This Field Controls

  • - Alias of fflags: accrued NV, DZ, OF, UF, and NX exception flags.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

4

NV

RW

Invalid-operation exception flag.

NV (bit 4) — Invalid-operation exception flag.

What This Field Controls

  • - Invalid-operation exception flag.

Common Values

00

The NV flag is clear.

11

The NV flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

3

DZ

RW

Divide-by-zero exception flag.

DZ (bit 3) — Divide-by-zero exception flag.

What This Field Controls

  • - Divide-by-zero exception flag.

Common Values

00

The DZ flag is clear.

11

The DZ flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

2

OF

RW

Overflow exception flag.

OF (bit 2) — Overflow exception flag.

What This Field Controls

  • - Overflow exception flag.

Common Values

00

The OF flag is clear.

11

The OF flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

1

UF

RW

Underflow exception flag.

UF (bit 1) — Underflow exception flag.

What This Field Controls

  • - Underflow exception flag.

Common Values

00

The UF flag is clear.

11

The UF flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

0

NX

RW

Inexact exception flag.

NX (bit 0) — Inexact exception flag.

What This Field Controls

  • - Inexact exception flag.

Common Values

00

The NX flag is clear.

11

The NX flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

Official Basis & Search Notes

fcsr is a RW CSR in user floating-point state csrs at 0x003. Check privilege and implemented extensions before interpreting its bit fields.

fcsr address, lowest access privilege, and access class are checked against the official CSR table: 0x003, User, RW.
Read it as part of user floating-point state csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Unprivileged ISA Manual, Section 21.2

What To Check First When Reading This CSR

  • - Table 73 lists this as a user-level read/write floating-point control and status CSR; U in the CSR address mapping is the lowest access privilege.
  • - fflags, frm, and fcsr have U as their lowest access privilege; more-privileged software may also use them under the CSR access rules.

Risk Checks Before Writing

  • - Bits 31:8 can be used by other standard extensions; standard software should preserve them. Without those extensions, writes are ignored and reads return zero.
  • - FSRM and FSFLAGS can update the frm and fflags portions of fcsr separately.

Put It Back Into A Real Flow

1

FRCSR copies the complete fcsr into rd; FSCSR swaps fcsr and writes its original value to rd.

2

When the other standard extensions are absent, writes to bits 31:8 are ignored and reads return zero; standard software should preserve these bits.

FAQ

Can fcsr be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records fcsr as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing fcsr?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.