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CSR Bit Fields

RISC-V fcsr CSR Register

Address 0x003Privilege UserAccess RW / 32User floating-point state CSRs

Floating-point control and status register; combines frm (rounding mode) and fflags (exception flags).

Related Search Terms
fcsr CSRfcsr 0x003fcsr fflags frmfloating point statusfloating point control CSRRISC-V fcsr
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:8FRM7:5RWFFLAGS4:0RW
Field Map

Understand fcsr By Bit Fields

7 key fields
7:5

FRM

RW

Floating-point dynamic rounding mode: 000 RNE, 001 RTZ, 010 RDN, 011 RUP, 100 RMM; 101/110 are reserved; 111 is reserved in frm/fcsr (DYN is only for instruction rm fields).

FRM (bits 7:5) — Floating-point dynamic rounding mode: 000 RNE, 001 RTZ, 010 RDN, 011 RUP, 100 RMM; 101/110 are reserved; 111 is reserved in frm/fcsr (DYN is only for instruction rm fields).

What This Field Controls

  • - Floating-point dynamic rounding mode: 000 RNE, 001 RTZ, 010 RDN, 011 RUP, 100 RMM; 101/110 are reserved; 111 is reserved in frm/fcsr (DYN is only for instruction rm fields).

Common Values

000RNE

Round to Nearest, ties to Even.

001RTZ

Round towards Zero.

010RDN

Round Down, toward negative infinity.

011RUP

Round Up, toward positive infinity.

100RMM

Round to Nearest, ties to Max Magnitude.

101Reserved

Reserved rounding-mode encoding.

110Reserved

Reserved rounding-mode encoding.

111DYN / Reserved

In an instruction rm field this selects dynamic rounding mode; in the frm CSR this encoding is reserved.

4:0

FFLAGS

RW

Accrued floating-point exception flags ordered as NV, DZ, OF, UF, NX.

FFLAGS (bits 4:0) — Accrued floating-point exception flags ordered as NV, DZ, OF, UF, NX.

What This Field Controls

  • - Accrued floating-point exception flags ordered as NV, DZ, OF, UF, NX.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

4

NV

RW

Invalid-operation exception flag.

NV (bit 4) — Invalid-operation exception flag.

What This Field Controls

  • - Invalid-operation exception flag.

Common Values

00

The NV exception flag is clear.

11

The NV exception flag is accrued/set; the RISC-V F extension requires software to check flags explicitly.

3

DZ

RW

Divide-by-zero exception flag.

DZ (bit 3) — Divide-by-zero exception flag.

What This Field Controls

  • - Divide-by-zero exception flag.

Common Values

00

The DZ exception flag is clear.

11

The DZ exception flag is accrued/set; the RISC-V F extension requires software to check flags explicitly.

2

OF

RW

Overflow exception flag.

OF (bit 2) — Overflow exception flag.

What This Field Controls

  • - Overflow exception flag.

Common Values

00

The OF exception flag is clear.

11

The OF exception flag is accrued/set; the RISC-V F extension requires software to check flags explicitly.

1

UF

RW

Underflow exception flag.

UF (bit 1) — Underflow exception flag.

What This Field Controls

  • - Underflow exception flag.

Common Values

00

The UF exception flag is clear.

11

The UF exception flag is accrued/set; the RISC-V F extension requires software to check flags explicitly.

0

NX

RW

Inexact exception flag.

NX (bit 0) — Inexact exception flag.

What This Field Controls

  • - Inexact exception flag.

Common Values

00

The NX exception flag is clear.

11

The NX exception flag is accrued/set; the RISC-V F extension requires software to check flags explicitly.

Official Basis & Search Notes

fcsr is a RW CSR in user floating-point state csrs at 0x003. Check privilege and implemented extensions before interpreting its bit fields.

fcsr address, lowest access privilege, and access class are checked against the official CSR table: 0x003, User, RW.
Read it as part of user floating-point state csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements fcsr; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x003 and the lowest access privilege (User) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads fcsr to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can fcsr be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records fcsr as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing fcsr?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.