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CSR Bit Fields

RISC-V fflags CSR Register

Address 0x001Privilege UserAccess RW / 32User floating-point state CSRs

Floating-point exception flags register; accrues IEEE-754 exceptions from FP operations.

Related Search Terms
fflags CSRfflags 0x001fflags exception flagsfflags NV DZ OF UF NXfloating point accrued flagsRISC-V fflags
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:5ReservedNX0RW
Field Map

Understand fflags By Bit Fields

6 key fields
XLEN-1:5

Reserved

Reserved

The separate fflags access exposes only fcsr[4:0]; all other bits are zero.

Reserved (bits XLEN-1:5) — The separate fflags access exposes only fcsr[4:0]; all other bits are zero.

What This Field Controls

  • - The separate fflags access exposes only fcsr[4:0]; all other bits are zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

4

NV

RW

Invalid-operation exception flag.

NV (bit 4) — Invalid-operation exception flag.

What This Field Controls

  • - Invalid-operation exception flag.

Common Values

00

The NV flag is clear.

11

The NV flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

3

DZ

RW

Divide-by-zero exception flag.

DZ (bit 3) — Divide-by-zero exception flag.

What This Field Controls

  • - Divide-by-zero exception flag.

Common Values

00

The DZ flag is clear.

11

The DZ flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

2

OF

RW

Overflow exception flag.

OF (bit 2) — Overflow exception flag.

What This Field Controls

  • - Overflow exception flag.

Common Values

00

The OF flag is clear.

11

The OF flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

1

UF

RW

Underflow exception flag.

UF (bit 1) — Underflow exception flag.

What This Field Controls

  • - Underflow exception flag.

Common Values

00

The UF flag is clear.

11

The UF flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

0

NX

RW

Inexact exception flag.

NX (bit 0) — Inexact exception flag.

What This Field Controls

  • - Inexact exception flag.

Common Values

00

The NX flag is clear.

11

The NX flag has accrued since software last reset the field; the base RISC-V ISA does not trap when it is set.

Official Basis & Search Notes

fflags is a RW CSR in user floating-point state csrs at 0x001. Check privilege and implemented extensions before interpreting its bit fields.

fflags address, lowest access privilege, and access class are checked against the official CSR table: 0x001, User, RW.
Read it as part of user floating-point state csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Unprivileged ISA Manual, Section 21.2

What To Check First When Reading This CSR

  • - Table 73 lists this as a user-level read/write floating-point control and status CSR; U in the CSR address mapping is the lowest access privilege.
  • - fflags, frm, and fcsr have U as their lowest access privilege; more-privileged software may also use them under the CSR access rules.

Risk Checks Before Writing

  • - FSFLAGS writes only the low five bits of rs1; software writes can reset or set accrued flags.
  • - Floating-point instructions accrue these flags; do not interpret them as automatic trap controls.

Put It Back Into A Real Flow

1

After floating-point operations, read fflags to inspect exception conditions accrued since software last reset the field.

2

FRFLAGS copies fflags into the low five bits of rd; FSFLAGS swaps the field and writes a new value from the low five bits of rs1.

FAQ

Can fflags be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records fflags as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing fflags?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.