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CSR Bit Fields

RISC-V frm CSR Register

Address 0x002Privilege UserAccess RW / 32User floating-point state CSRs

Floating-point dynamic rounding mode register; specifies the rounding mode for FP operations.

Related Search Terms
frm CSRfrm 0x002frm rounding modedynamic rounding modeRISC-V frmfloating point rounding CSR
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:3FRM2:0RW
Field Map

Understand frm By Bit Fields

1 key fields
2:0

FRM

RW

Floating-point dynamic rounding mode: 000 RNE, 001 RTZ, 010 RDN, 011 RUP, 100 RMM; 101/110 are reserved; 111 is reserved in frm/fcsr (DYN is only for instruction rm fields).

FRM (bits 2:0) — Floating-point dynamic rounding mode: 000 RNE, 001 RTZ, 010 RDN, 011 RUP, 100 RMM; 101/110 are reserved; 111 is reserved in frm/fcsr (DYN is only for instruction rm fields).

What This Field Controls

  • - Floating-point dynamic rounding mode: 000 RNE, 001 RTZ, 010 RDN, 011 RUP, 100 RMM; 101/110 are reserved; 111 is reserved in frm/fcsr (DYN is only for instruction rm fields).

Common Values

000RNE

Round to Nearest, ties to Even.

001RTZ

Round towards Zero.

010RDN

Round Down, toward negative infinity.

011RUP

Round Up, toward positive infinity.

100RMM

Round to Nearest, ties to Max Magnitude.

101Reserved

Reserved rounding-mode encoding.

110Reserved

Reserved rounding-mode encoding.

111DYN / Reserved

In an instruction rm field this selects dynamic rounding mode; in the frm CSR this encoding is reserved.

Official Basis & Search Notes

frm is a RW CSR in user floating-point state csrs at 0x002. Check privilege and implemented extensions before interpreting its bit fields.

frm address, lowest access privilege, and access class are checked against the official CSR table: 0x002, User, RW.
Read it as part of user floating-point state csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements frm; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x002 and the lowest access privilege (User) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads frm to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can frm be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records frm as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing frm?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.