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CSR Bit Fields

RISC-V frm CSR Register

Address 0x002Privilege UserAccess RW / 32User floating-point state CSRs

Floating-point dynamic rounding mode register; specifies the rounding mode for FP operations.

Related Search Terms
frm CSRfrm 0x002frm rounding modedynamic rounding modeRISC-V frmfloating point rounding CSR
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:3ReservedFRM2:0RW
Field Map

Understand frm By Bit Fields

2 key fields
XLEN-1:3

Reserved

Reserved

The separate frm access exposes only fcsr[7:5]; all other bits are zero.

Reserved (bits XLEN-1:3) — The separate frm access exposes only fcsr[7:5]; all other bits are zero.

What This Field Controls

  • - The separate frm access exposes only fcsr[7:5]; all other bits are zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

2:0

FRM

RW

Dynamic rounding mode. 101, 110, and 111 are reserved encodings in frm/fcsr; 111 (DYN) selects frm only in an instruction rm field.

FRM (bits 2:0) — Dynamic rounding mode. 101, 110, and 111 are reserved encodings in frm/fcsr; 111 (DYN) selects frm only in an instruction rm field.

What This Field Controls

  • - Dynamic rounding mode. 101, 110, and 111 are reserved encodings in frm/fcsr; 111 (DYN) selects frm only in an instruction rm field.

Common Values

000RNE

Round to Nearest, ties to Even.

001RTZ

Round towards Zero.

010RDN

Round Down (towards negative infinity).

011RUP

Round Up (towards positive infinity).

100RMM

Round to Nearest, ties to Max Magnitude.

101Reserved

Reserved for future use.

110Reserved

Reserved for future use.

111Reserved

Reserved in frm/fcsr; DYN applies only to an instruction rm field.

Official Basis & Search Notes

frm is a RW CSR in user floating-point state csrs at 0x002. Check privilege and implemented extensions before interpreting its bit fields.

frm address, lowest access privilege, and access class are checked against the official CSR table: 0x002, User, RW.
Read it as part of user floating-point state csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Unprivileged ISA Manual, Section 21.2

What To Check First When Reading This CSR

  • - Table 73 lists this as a user-level read/write floating-point control and status CSR; U in the CSR address mapping is the lowest access privilege.
  • - fflags, frm, and fcsr have U as their lowest access privilege; more-privileged software may also use them under the CSR access rules.

Risk Checks Before Writing

  • - Do not use reserved dynamic encodings 101, 110, or 111 as frm values; behavior of floating-point instructions that depend on them is reserved.
  • - Changing frm can cause an implementation to serialize its pipeline.

Put It Back Into A Real Flow

1

When an instruction has rm=111, it selects the dynamic rounding mode in frm; other static rm encodings are specified by the instruction.

2

FRRM copies frm into the low three bits of rd; FSRM swaps the field and writes a new value from the low three bits of rs1.

FAQ

Can frm be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records frm as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing frm?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.