RISC-V pmpcfg8 CSR Register

PMP entry 32 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr32 may still be locked by a later locked TOR entry.

PMP entry 32 is locked; writes to pmp32cfg and pmpaddr32 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr31 is also locked.

PMP entry 32 is disabled and matches no addresses.

PMP entry 32 uses top-of-range matching; the upper bound comes from pmpaddr32, and the lower bound comes from pmpaddr31.

PMP entry 32 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 32 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr32.

PMP entry 32 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 32 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 32 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 32 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 32 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 32 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 33 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr33 may still be locked by a later locked TOR entry.

PMP entry 33 is locked; writes to pmp33cfg and pmpaddr33 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr32 is also locked.

PMP entry 33 is disabled and matches no addresses.

PMP entry 33 uses top-of-range matching; the upper bound comes from pmpaddr33, and the lower bound comes from pmpaddr32.

PMP entry 33 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 33 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr33.

PMP entry 33 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 33 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 33 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 33 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 33 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 33 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 34 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr34 may still be locked by a later locked TOR entry.

PMP entry 34 is locked; writes to pmp34cfg and pmpaddr34 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr33 is also locked.

PMP entry 34 is disabled and matches no addresses.

PMP entry 34 uses top-of-range matching; the upper bound comes from pmpaddr34, and the lower bound comes from pmpaddr33.

PMP entry 34 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 34 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr34.

PMP entry 34 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 34 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 34 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 34 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 34 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 34 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 35 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr35 may still be locked by a later locked TOR entry.

PMP entry 35 is locked; writes to pmp35cfg and pmpaddr35 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr34 is also locked.

PMP entry 35 is disabled and matches no addresses.

PMP entry 35 uses top-of-range matching; the upper bound comes from pmpaddr35, and the lower bound comes from pmpaddr34.

PMP entry 35 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 35 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr35.

PMP entry 35 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 35 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 35 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 35 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 35 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 35 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 36 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr36 may still be locked by a later locked TOR entry.

PMP entry 36 is locked; writes to pmp36cfg and pmpaddr36 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr35 is also locked.

PMP entry 36 is disabled and matches no addresses.

PMP entry 36 uses top-of-range matching; the upper bound comes from pmpaddr36, and the lower bound comes from pmpaddr35.

PMP entry 36 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 36 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr36.

PMP entry 36 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 36 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 36 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 36 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 36 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 36 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 37 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr37 may still be locked by a later locked TOR entry.

PMP entry 37 is locked; writes to pmp37cfg and pmpaddr37 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr36 is also locked.

PMP entry 37 is disabled and matches no addresses.

PMP entry 37 uses top-of-range matching; the upper bound comes from pmpaddr37, and the lower bound comes from pmpaddr36.

PMP entry 37 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 37 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr37.

PMP entry 37 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 37 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 37 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 37 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 37 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 37 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 38 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr38 may still be locked by a later locked TOR entry.

PMP entry 38 is locked; writes to pmp38cfg and pmpaddr38 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr37 is also locked.

PMP entry 38 is disabled and matches no addresses.

PMP entry 38 uses top-of-range matching; the upper bound comes from pmpaddr38, and the lower bound comes from pmpaddr37.

PMP entry 38 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 38 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr38.

PMP entry 38 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 38 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 38 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 38 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 38 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 38 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 39 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr39 may still be locked by a later locked TOR entry.

PMP entry 39 is locked; writes to pmp39cfg and pmpaddr39 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr38 is also locked.

PMP entry 39 is disabled and matches no addresses.

PMP entry 39 uses top-of-range matching; the upper bound comes from pmpaddr39, and the lower bound comes from pmpaddr38.

PMP entry 39 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 39 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr39.

PMP entry 39 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 39 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 39 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 39 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 39 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 39 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.