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CSR Bit Fields

RISC-V scontext CSR Register

Address 0x5A8Privilege SupervisorAccess SRW / XLEN (bits 63:32 are 0 on RV64)Debug, trace, and context CSRs

scontext (0x5A8) is the supervisor-mode context CSR provided by the Sdtrig extension and listed in the official CSR table's Debug/Trace Registers group.

Related Search Terms
scontext CSRscontext 0x5A8supervisor context CSRscontext SRWSdtrig scontextmstateen0 CONTEXThstateen0 CONTEXT
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
RO063:32RO 0data31:0WARL
Field Map

Understand scontext By Bit Fields

2 key fields
31:0

data

WARL

A context number written by supervisor software, usable for triggers that fire only in that context. An implementation may tie any number of this field's high bits to 0; the specification recommends 16 implemented bits on RV32 and 32 on RV64. Reset is 0.

data (bits 31:0) — A context number written by supervisor software, usable for triggers that fire only in that context. An implementation may tie any number of this field's high bits to 0; the specification recommends 16 implemented bits on RV32 and 32 on RV64. Reset is 0.

What This Field Controls

  • - A context number written by supervisor software, usable for triggers that fire only in that context. An implementation may tie any number of this field's high bits to 0; the specification recommends 16 implemented bits on RV32 and 32 on RV64. Reset is 0.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
63:32

RO0

RO 0

In the RV64 layout, data occupies bits 31:0 and bits 63:32 are 0.

RO0 (bits 63:32) — In the RV64 layout, data occupies bits 31:0 and bits 63:32 are 0.

What This Field Controls

  • - In the RV64 layout, data occupies bits 31:0 and bits 63:32 are 0.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

scontext is the Sdtrig supervisor-mode context CSR at 0x5A8 with the SRW access class in the official CSR table.

The official CSR table lists scontext as the SRW supervisor-mode context register at 0x5A8 in Debug/Trace Registers.
scontext is optional. Its data[31:0] is a WARL context number that resets to 0; bits 63:32 are 0 on RV64.
mstateen0.CONTEXT controls access to Sdtrig's scontext/hcontext, and hstateen0.CONTEXT controls access to scontext.
When V=1, scontext has no matching VS CSR; the privileged manual says it retains its usual function and accessibility, with contents swapped by hypervisor software as needed.
RISC-V Privileged Architecture ManualRISC-V Debug Specification 1.0, Sdtrig Section 5.7.8

What To Check First When Reading This CSR

  • - The official CSR table lists scontext as the SRW supervisor-mode context register at 0x5A8 in Debug/Trace Registers.
  • - scontext is optional and accessible from S/HS-mode, VS-mode, M-mode, and Debug Mode; its data field is WARL and resets to 0.
  • - scontext is provided by Sdtrig; mstateen0.CONTEXT and hstateen0.CONTEXT control access to it.
  • - When V=1, scontext has no matching VS CSR; it retains its usual function and accessibility with VS/VU substituted for HS/U, and hypervisor software swaps its contents as needed.

Risk Checks Before Writing

  • - scontext is optional. An implementation may tie any number of high data bits to 0; read back after writing to determine the WARL value accepted by the implementation.

Put It Back Into A Real Flow

1

Confirm that the target implements Sdtrig scontext state.

2

Confirm the current mode is S/HS-mode, VS-mode, M-mode, or Debug Mode, and check the mstateen0.CONTEXT and hstateen0.CONTEXT access gates.

3

Write and read back the data context number to determine the WARL value accepted by the implementation.

4

When V=1, manage supervisor state with no matching VS CSR in software as described by the privileged manual.

FAQ

Which state-enable bits control scontext access?

The privileged manual states that mstateen0.CONTEXT controls access to Sdtrig's scontext/hcontext, and hstateen0.CONTEXT controls access to scontext.

Does scontext have a VS copy when V=1?

No. The privileged manual lists scontext among supervisor CSRs with no matching VS CSR; when V=1 it retains its usual function and accessibility, with contents manually swapped by hypervisor software as needed.