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CSR Bit Fields

RISC-V spmpenh CSR Register

Address 0x193Privilege SupervisorAccess Supervisor RW (WARL, RV32 only) / RV32 only: high-half / 32-bit; not applicable to RV64Supervisor SPMP CSRs

spmpenh (0x193) is the 32-bit RV32 high-half WARL CSR defined by Sspmpen, aliasing spmpen[63:32].

Related Search Terms
spmpenh CSRspmpenh 0x193RV32 spmpenhspmpen high halfSPMP entries 32-63
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
spmpen[63:32]31:0WARL/locked-entry bits are RO
Field Map

Understand spmpenh By Bit Fields

1 key fields
31:0

spmpen[63:32]

WARL/locked-entry bits are RO

RV32 only: alias of the upper 32 bits of spmpen, corresponding to SPMP entries 32-63. Only bits for delegated/implemented entries are effective; out-of-range writes are ignored.

spmpen[63:32] (bits 31:0) — RV32 only: alias of the upper 32 bits of spmpen, corresponding to SPMP entries 32-63. Only bits for delegated/implemented entries are effective; out-of-range writes are ignored.

What This Field Controls

  • - RV32 only: alias of the upper 32 bits of spmpen, corresponding to SPMP entries 32-63. Only bits for delegated/implemented entries are effective; out-of-range writes are ignored.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

spmpenh aliases spmpen[63:32] on RV32 and combines with the low half in spmpen to form the 64-bit SPMP enable bitmap.

Sspmpen v0.9.2 defines spmpenh at 0x193 for RV32 only.
Each bit controls whether the corresponding high-numbered entry participates in matching, but the entry's A field must still be nonzero.
The official Recommended Programming Guidelines require an uninterruptible low/high-half update in the RV32 static-configuration model; specification-defined fence ordering is also required after writes.
RISC-V S-level Physical Memory Protection v0.9.2 (Frozen)Sspmpen v0.9.2 - SPMP entry activationSspmp v0.9.2 - S-level Physical Memory Protection CSRsSspmp v0.9.2 - Recommended Programming Guidelines

What To Check First When Reading This CSR

  • - spmpenh is present only on RV32 with the optional Sspmpen extension.
  • - Bit i corresponds to SPMP entry 32+i, whose activation also requires spmpcfg[32+i].A to be nonzero.
  • - A bit corresponding to a locked entry is read-only.

Risk Checks Before Writing

  • - In the official static-configuration context-switch model, RV32 with more than 32 SPMP entries must update spmpen and spmpenh as an uninterruptible sequence to guarantee complete protection.
  • - Writes are not ordered with subsequent memory accesses; execute the required SFENCE.VMA before relying on the new configuration.

Put It Back Into A Real Flow

1

First configure the target entry among entries 32-63 with its address, permissions, and nonzero A field.

2

When the static-configuration model switches a task using more than 32 entries, update spmpen and spmpenh in a non-preemptible critical section.

3

Execute the required SFENCE.VMA before subsequent S/U accesses.

FAQ

Does spmpenh exist on RV64?

No. spmpenh is the RV32-only 32-bit high-half CSR aliasing spmpen[63:32]; RV64 uses the 64-bit spmpen CSR directly.