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CSR Bit Fields

RISC-V spmpen CSR Register

Address 0x183Privilege SupervisorAccess Supervisor RW (WARL) / SXLEN: low 32 bits on RV32; 64 bits on RV64Supervisor SPMP CSRs

spmpen (0x183) is the supervisor WARL CSR defined by the Frozen Sspmpen extension; each bit controls whether the corresponding SPMP entry participates in matching and permission checks.

Related Search Terms
spmpen CSRspmpen 0x183SspmpenSPMP entry enablespmpen WARLSPMP context switch
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
spmpen[63:32]63:32WARL/locked-entry bits are ROspmpen[31:0]31:0WARL/locked-entry bits are RO
Field Map

Understand spmpen By Bit Fields

2 key fields
31:0

spmpen[31:0]

WARL/locked-entry bits are RO

Enable bits for SPMP entries 0-31 on RV32 and the low 32 bits of the full spmpen CSR on RV64. Only bits corresponding to delegated/implemented entries are effective; out-of-range writes are ignored.

spmpen[31:0] (bits 31:0) — Enable bits for SPMP entries 0-31 on RV32 and the low 32 bits of the full spmpen CSR on RV64. Only bits corresponding to delegated/implemented entries are effective; out-of-range writes are ignored.

What This Field Controls

  • - Enable bits for SPMP entries 0-31 on RV32 and the low 32 bits of the full spmpen CSR on RV64. Only bits corresponding to delegated/implemented entries are effective; out-of-range writes are ignored.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
63:32

spmpen[63:32]

WARL/locked-entry bits are RO

RV64 only: enable bits for SPMP entries 32-63. RV32 accesses the same logical bit range through spmpenh.

spmpen[63:32] (bits 63:32) — RV64 only: enable bits for SPMP entries 32-63. RV32 accesses the same logical bit range through spmpenh.

What This Field Controls

  • - RV64 only: enable bits for SPMP entries 32-63. RV32 accesses the same logical bit range through spmpenh.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

spmpen is the Sspmpen active-entry bitmap. Entry i participates in SPMP matching and permission checks only when spmpen[i]=1 and spmpcfg[i].A is nonzero.

Sspmpen v0.9.2 defines 0x183 as a WARL CSR: 64 bits on RV64, with RV32 using spmpen/spmpenh for the low/high halves.
An enable bit for a locked entry is read-only, and writes above the delegated SPMP entry range are ignored.
Writes are not ordered with subsequent memory accesses and require the memory-management fence specified by Sspmp.
RISC-V S-level Physical Memory Protection v0.9.2 (Frozen)Sspmpen v0.9.2 - SPMP entry activationSspmp v0.9.2 - S-level Physical Memory Protection CSRsSmpmpdeleg v0.9.2 - PMP/SPMP resource sharingSspmp v0.9.2 - Recommended Programming Guidelines

What To Check First When Reading This CSR

  • - spmpen is present only with the optional Sspmpen extension; the v0.9.2 specification is Frozen.
  • - A set bit alone does not activate an entry; the corresponding spmpcfg[i].A must also be nonzero.
  • - The spmpen bit corresponding to a locked SPMP entry is read-only.

Risk Checks Before Writing

  • - A spmpen write is not ordered with subsequent memory accesses; subsequent S/U accesses require SFENCE.VMA with rs1=x0 and rs2=x0 under the Sspmp access-method rule.
  • - In the official static-configuration context-switch model, RV32 with more than 32 SPMP entries must update spmpen and spmpenh as an uninterruptible sequence to guarantee complete protection.

Put It Back Into A Real Flow

1

First configure the target spmpcfg/spmpaddr entries and ensure their A fields are nonzero.

2

Use the spmpen bitmap to select entries that participate in matching and permission checks.

3

Execute the required SFENCE.VMA ordering before S/U memory accesses rely on the new configuration.

FAQ

Does spmpen[i]=1 always activate SPMP entry i?

No. Entry i is active only when spmpen[i]=1 and spmpcfg[i].A is nonzero; if the entry is locked, its corresponding spmpen bit also becomes read-only.