RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V srmcfg CSR Register

Address 0x181Privilege SupervisorAccess RW / SXLENSupervisor resource-management CSRs

srmcfg (0x181) is the Ssqosid Supervisor Resource Management Configuration CSR, using WARL RCID and MCID fields to configure resource-control and monitoring identifiers.

Related Search Terms
srmcfg CSRsrmcfg 0x181SsqosidRCIDMCIDresource management
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
WPRI63:32WPRIWPRI31:28WPRIMCID27:16WARLWPRI15:12WPRIRCID11:0WARL
Field Map

Understand srmcfg By Bit Fields

5 key fields
11:0

RCID

WARL

Resource Control ID carried with hart requests to shared resource controllers to select enforced resource-allocation limits. The implemented legal-value set is determined by WARL behavior.

RCID (bits 11:0) — Resource Control ID carried with hart requests to shared resource controllers to select enforced resource-allocation limits. The implemented legal-value set is determined by WARL behavior.

What This Field Controls

  • - Resource Control ID carried with hart requests to shared resource controllers to select enforced resource-allocation limits. The implemented legal-value set is determined by WARL behavior.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
15:12

WPRI

WPRI

Reserved; software should preserve these bits when writing and ignore their values when reading.

WPRI (bits 15:12) — Reserved; software should preserve these bits when writing and ignore their values when reading.

What This Field Controls

  • - Reserved; software should preserve these bits when writing and ignore their values when reading.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
27:16

MCID

WARL

Monitoring Counter ID carried with hart requests to identify a counter that monitors resource usage. The implemented legal-value set is determined by WARL behavior.

MCID (bits 27:16) — Monitoring Counter ID carried with hart requests to identify a counter that monitors resource usage. The implemented legal-value set is determined by WARL behavior.

What This Field Controls

  • - Monitoring Counter ID carried with hart requests to identify a counter that monitors resource usage. The implemented legal-value set is determined by WARL behavior.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
31:28

WPRI

WPRI

Reserved; software should preserve these bits when writing and ignore their values when reading.

WPRI (bits 31:28) — Reserved; software should preserve these bits when writing and ignore their values when reading.

What This Field Controls

  • - Reserved; software should preserve these bits when writing and ignore their values when reading.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
63:32

WPRI

WPRI

Upper 32 reserved bits when SXLEN=64; software should preserve them when writing and ignore their values when reading.

WPRI (bits 63:32) — Upper 32 reserved bits when SXLEN=64; software should preserve them when writing and ignore their values when reading.

What This Field Controls

  • - Upper 32 reserved bits when SXLEN=64; software should preserve them when writing and ignore their values when reading.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

srmcfg configures RCID and MCID for shared-resource requests from the hart. RCID determines the resource-allocation limits to enforce; MCID identifies a counter that monitors resource usage.

Ssqosid defines srmcfg as an SXLEN-bit read/write register.
Figures 45 and 46 define WARL RCID[11:0] and MCID[27:16], with WPRI at [15:12], [31:28], and RV64 [63:32].
By default, RCID/MCID in srmcfg apply to software execution at all privilege levels on that hart.
RISC-V Privileged Architecture Manual v20260120 - CSR tableRISC-V Privileged Architecture Manual v20260120 - Ssqosid 12.13.1RISC-V Privileged Architecture Manual v20260120 - Smstateen 4.2 SRMCFG

What To Check First When Reading This CSR

  • - srmcfg is an SXLEN-bit SRW CSR at address 0x181 introduced by Ssqosid; Ssqosid does not require S-mode to be implemented.
  • - RCID and MCID are both WARL; a readback reflects the legal encoding selected by the implementation for the written value.
  • - The specification suggests resetting RCID to 0 to match resource controllers' default association of all capacity with RCID=0; the MCID reset value does not affect functionality and may be implementation-defined.
  • - By default, the RCID and MCID configured in srmcfg apply to software execution at every privilege level on the hart; future extensions may override this behavior.

Risk Checks Before Writing

  • - RCID and MCID are WARL; read back after writing to confirm the legal value accepted by the implementation.
  • - If Smstateen and Ssqosid are both implemented, access to srmcfg below M-mode raises an illegal-instruction exception when mstateen0.SRMCFG=0.
  • - If mstateen0.SRMCFG=1, or Smstateen is not implemented, access to srmcfg when V=1 raises a virtual-instruction exception.
  • - Preserve WPRI[15:12] and WPRI[31:28] when writing, plus WPRI[63:32] on RV64.

Put It Back Into A Real Flow

1

Choose RCID and MCID according to the platform resource-control and monitoring policy.

2

After writing srmcfg, read it back to confirm the legal RCID/MCID values accepted by the WARL fields.

3

In virtualization or state-enable scenarios, first confirm controls such as mstateen0.SRMCFG allow the current context to use this CSR.

FAQ

Is srmcfg a page-table or PMP CSR?

No. It is an Ssqosid resource-management/QoS identifier CSR, not an address-translation or PMP region control CSR.