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CSR Bit Fields

RISC-V stopei CSR Register

Address 0x15CPrivilege SupervisorAccess RW / XLENSupervisor AIA, timer, and indirect interrupt CSRs

stopei (0x15C) is the AIA/IMSIC Supervisor top external interrupt CSR, reporting and claiming the highest-priority pending-and-enabled external interrupt in the supervisor interrupt file.

Related Search Terms
stopei CSRstopei 0x15CAIA IMSICtop external interruptinterrupt claimSEI
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
ReservedZero63:0RO 0
Field Map

Understand stopei By Bit Fields

3 key fields
26:16

IID

RO / write claims

On read, reports the identity of the highest-priority pending-and-enabled external interrupt; writing stopei clears the pending bit indicated by the current readable value.

IID (bits 26:16) — On read, reports the identity of the highest-priority pending-and-enabled external interrupt; writing stopei clears the pending bit indicated by the current readable value.

What This Field Controls

  • - On read, reports the identity of the highest-priority pending-and-enabled external interrupt; writing stopei clears the pending bit indicated by the current readable value.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
10:0

IPRIO

RO

Interrupt priority in the returned value; in AIA/IMSIC it is the same as the identity.

IPRIO (bits 10:0) — Interrupt priority in the returned value; in AIA/IMSIC it is the same as the identity.

What This Field Controls

  • - Interrupt priority in the returned value; in AIA/IMSIC it is the same as the identity.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
XLEN-1:27,15:11

ReservedZero

RO 0

Other bits read as zero.

ReservedZero (bits XLEN-1:27,15:11) — Other bits read as zero.

What This Field Controls

  • - Other bits read as zero.

Common Values

stopei reserved-zero bits
0Read-only zero

These bits read as zero in the AIA/IMSIC stopei format; software must not write them or depend on a meaning for 1.

↗Open Official Manual
Official Basis & Search Notes

stopei is the top-external-interrupt view of the IMSIC supervisor interrupt file. Its read value depends on pending, enable, and eithreshold state; a write claims the interrupt indicated by the current read value.

A read returns zero when no external interrupt is both pending and enabled above the threshold.
Bits 26:16 are the interrupt identity and bits 10:0 are the priority.
AIA explicitly warns against separate read and write claiming unless the eip array is used to clear the exact pending bit.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Advanced Interrupt Architecture - IMSIC CSRsRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - First confirm that the hart implements the extension containing stopei; unimplemented or insufficiently privileged CSR accesses raise an illegal-instruction exception.
  • - Use address 0x15C, the lowest access privilege, and the official access class to decide whether software may access it directly.
  • - Do not assume fixed values for reserved, WPRI, WARL, or WLRL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

  • - Usually claim stopei with a CSR instruction that reads and writes simultaneously; a separate read then write can clear a higher-priority interrupt that appears between the two instructions.
  • - When the current stopei value is zero, a write has no effect.

Put It Back Into A Real Flow

1

In a supervisor external-interrupt handler, read stopei to obtain the top interrupt identity.

2

Claim it with the same CSR read/write operation; shift the returned value right by 16 to get the minor identity.

3

Call the matching external-interrupt service routine; if claiming must be separate, clear the eip pending bit through siselect/sireg.

FAQ

Is stopei affected by sie.SEIE?

The top value read from stopei is not affected by enable CSRs such as sie/hie/vsie; those affect delivery, while stopei reflects pending-and-enabled state inside the interrupt file.

Does the written value to stopei matter?

The written value is ignored; the pending bit cleared is determined by the current readable stopei value at the time of the write.