RISC-V Instruction Encoder
Enter a RISC-V assembly instruction and inspect the 32-bit machine word, hex value, binary bits, and field breakdown for learning opcode, funct, register fields, and immediate encoding. The current tool covers a verified integer-instruction subset.
Input
Supports a verified subset of 32-bit R/I/S/B/U/J integer instructions with x0-x31 and ABI register names, decimal/hex immediates, load/store offset(base) operands, common CSR names, and selected RV64 instructions. Pseudo instructions, labels, multi-line assembly, compressed instructions, A/F/D/C/V extensions, and most privileged or FENCE instructions are not supported here.
Encoding Result
Built-in Accuracy Checks
These fixed examples cover R/I/S/B/U/J formats and act as regression checks for the encoder's core paths.
This page is organized with reference to the official RISC-V documents below for architecture, ABI, CSR, and pseudo-instruction notes; platform or OS ABI differences still need to be checked against their own specifications.
Base integer ISA, RV32/RV64, instruction formats, load/store, control flow, and atomic instruction semantics.
Privilege modes, trap entry/return, CSRs, address translation, PMP, and interrupt-related architectural state.
Assembly syntax, pseudo-instructions, common expansions, register names, and programmer-visible conventions.
Procedure calling convention, register preservation, stack alignment, ELF, DWARF, and relocation rules.