Does AES32ESMI use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES32ESMI
RISC-V AES32ESMI Instruction Details
Instruction ManualI-typeAES middle-round encrypt byte step: select a byte from rs2 by bs, apply SubBytes/MixColumns, XOR with rs1
Instruction Syntax
aes32esmi rd, rs1, rs2, bs
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZkneCrypto & Security
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
AES32ESMI uses opcode 0010011 (0x13), funct3 001, funct7 1010011. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 0010011 (0x13)
funct3: 001 (0x1)
funct7: 1010011 (0x53)
Instruction Behavior
aes32esmi is a Zkne scalar AES middle-round encrypt instruction for the 32-bit datapath on RV32/RV64. It selects a byte from rs2 using bs, applies the AES forward S-box and MixColumns-related transform, rotates the result into the byte position selected by bs, XORs it with rs1, and writes rd.
Quick Understanding & Search Notes
AES32ESMI is a Zkne scalar cryptography instruction for AES middle-round encrypt byte step. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
It selects one byte from rs2 using bs, applies the forward AES S-box and partial MixColumns, then XORs with rs1.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
bs selects a byte from rs2[31:0], and the 32-bit result is sign-extended into rd.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «aes32esmi a0, a1, a2, 0».
Data Protection
Understand this scenario with real code like «aes32esmi a0, a1, a2, 0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
bs selects the byte index (0-3) in rs2[31:0]; rs1 is the XOR source.
4 executions needed for one full AES-128 round.
FAQ
Is AES32ESMI a complete algorithm implementation?
No. It is a low-level step from AES, SHA, SM3, or SM4; software still combines instructions with the algorithm schedule, round constants, or round keys.