Does AES32DSMI use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES32DSMI
RISC-V AES32DSMI Instruction Details
Instruction ManualR-type (OP with bs in bits 31:30)AES middle-round decrypt byte step: select a byte from rs2 by bs, apply InvSubBytes/InvMixColumns, XOR with rs1
Instruction Syntax
aes32dsmi rd, rs1, rs2, bs
Syntax is rd, rs1, rs2, bs; bs is a two-bit byte selector, 0–3. Registers select x0–x31 or ABI names, with no rs3.
32-bit OP encoding: bits31:30=bs, bits29:25=10111, funct3=000, opcode=0110011.
RV32 only, requiring Zknd (also included in Zkn/Zk). Select an rs2 byte using bs, apply the inverse S-box and partial inverse MixColumn, rotate left by bs×8 within 32 bits, then XOR with rs1.
x0 sources are zero and rd=x0 discards writeback; overlap reads pre-execution source values, and equal sources have equal values. This instruction must have data-independent execution latency.
ZkndCrypto & Security
Instruction Behavior
aes32dsmi is an RV32 scalar AES middle-round decrypt instruction in Zknd. It selects a byte from rs2[31:0] using bs, applies the AES inverse S-box and partial inverse MixColumn, rotates the result left into the position selected by bs, XORs it with rs1[31:0], and writes rd.
AES32DSMI Decode And Execute Animation
Bounded teaching inputs follow the local official ISA formulas; this does not model a complete AES round, round-key XOR, or microarchitecture.
aes32dsmi
Execution Context
XLEN is fixed at 32; this animation rejects RV64-sized values. A destination that is not a source starts at 0; sources are read before writeback.
byte select
fixed
source state
source state
fixed
destination
OP
31..30
bs=01
29..25
10111
24..20
rs2=x12
19..15
rs1=x11
14..12
000
11..7
rd=x10
6..0
0110011
Execution Data Path
rs1[31:0]
0x11223344
rs2[31:0]
0xA1B2C3D4
si
0xC3
aes_sbox_inv(si)
0x33
aes_mixcolumn_byte_inv(so)
0xD67CB029
rol32(contribution, shamt)
0x7CB029D6
Current Step
Decode AES32 OP fields and bs
bits 31..30 are bs, bits 29..25 are 10111; funct3=000 and OP=0110011. This encoding is RV32-only.
encoding: 0x6EC58533
syntax: aes32dsmi a0(x10), a1(x11), a2(x12), 1
syntax: aes32dsmi a0(x10), a1(x11), a2(x12), 1
Architectural Result
a0(x10) = 0x00000000
This animation shows only official ISA fields and architectural state, not a particular CPU pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
AES32DSMI processes one byte of rs2: bs=0..3 selects the byte, inverse S-box and a partial inverse MixColumn forms a 32-bit contribution, then a left rotation by bs×8 and XOR with rs1 produce rd. It is not a complete AES decryption round.
shamt=bs×8; select a byte from rs2[31:0], apply the inverse S-box and a partial inverse MixColumn, rotate left by shamt within 32 bits, then XOR with rs1[31:0].
Operands use integer X registers; this instruction must have execution latency independent of its input data values.
This instruction is defined only for RV32 and requires Zknd; bs is a 2-bit field with values 0..3, and the result is written to 32-bit integer rd.
Common Usage Scenarios
Crypto & Security
RV32 with the required extension enabled; a1=0x11223344, a2=0xA1B2C3D4, bs=0: select 0xD4 from rs2, apply this instruction's S-box and partial MixColumn, rotate by 0, then XOR with a1, giving a0=0xF297E2DA. This is one byte-combination step.
Data Protection
RV32 with the required extension enabled; a1=0x11223344, a2=0xA1B2C3D4, bs=0: select 0xD4 from rs2, apply this instruction's S-box and partial MixColumn, rotate by 0, then XOR with a1, giving a0=0xF297E2DA. This is one byte-combination step.
Pre-Use Checklist
Syntax Check
- Syntax is rd, rs1, rs2, bs; bs is a two-bit byte selector, 0–3. Registers select x0–x31 or ABI names, with no rs3.
- 32-bit OP encoding: bits31:30=bs, bits29:25=10111, funct3=000, opcode=0110011.
Semantic Check
- RV32 only, requiring Zknd (also included in Zkn/Zk). Select an rs2 byte using bs, apply the inverse S-box and partial inverse MixColumn, rotate left by bs×8 within 32 bits, then XOR with rs1.
- x0 sources are zero and rd=x0 discards writeback; overlap reads pre-execution source values, and equal sources have equal values. This instruction must have data-independent execution latency.
Pitfalls / Common Confusions
bs selects the byte index (0-3) in rs2[31:0]; rs1 is the XOR source.
Middle round includes InvMixColumns; final round (aes32dsi) does not.
FAQ
Is AES32DSMI a complete algorithm implementation?
No. It performs one architecturally defined AES byte step; software still combines instructions and round keys in algorithm order.