Does AES32DSMI use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES32DSMI
RISC-V AES32DSMI Instruction Details
Instruction ManualR-type (OP with bs in bits 31:30)AES middle-round decrypt byte step: select a byte from rs2 by bs, apply InvSubBytes/InvMixColumns, XOR with rs1
Instruction Syntax
aes32dsmi rd, rs1, rs2, bs
Operand Breakdown
This is a R-type (OP with bs in bits 31:30)-format instruction. Confirm operand positions based on the assembly syntax.
ZkndCrypto & Security
Instruction Behavior
aes32dsmi is an RV32 scalar AES middle-round decrypt instruction in Zknd. It selects a byte from rs2[31:0] using bs, applies the AES inverse S-box and partial inverse MixColumn, rotates the result left into the position selected by bs, XORs it with rs1[31:0], and writes rd.
AES32DSMI Decode And Execute Animation
Bounded teaching inputs follow the local official ISA formulas; this does not model a complete AES round, round-key XOR, or microarchitecture.
aes32dsmi
Execution Context
XLEN is fixed at 32; this animation rejects RV64-sized values.
byte select
fixed
source state
source state
fixed
destination
OP
31..30
bs=01
29..25
10111
24..20
rs2=x12
19..15
rs1=x11
14..12
000
11..7
rd=x10
6..0
0110011
Execution Data Path
rs1[31:0]
0x11223344
rs2[31:0]
0xA1B2C3D4
si
0xC3
aes_sbox_inv(si)
0x33
aes_mixcolumn_byte_inv(so)
0xD67CB029
rol32(contribution, shamt)
0x7CB029D6
Current Step
Decode AES32 OP fields and bs
bits 31..30 are bs, bits 29..25 are 10111; funct3=000 and OP=0110011. This encoding is RV32-only.
encoding: 0x6EC58533
syntax: aes32dsmi a0(x10), a1(x11), a2(x12), 1
syntax: aes32dsmi a0(x10), a1(x11), a2(x12), 1
Architectural Result
a0(x10) = 0x6D921A92
This animation shows only official ISA fields and architectural state, not a particular CPU pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
AES32DSMI is a Zknd scalar cryptography instruction for AES middle-round decrypt byte step. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
It selects one byte from rs2 using bs, applies the inverse AES S-box and partial InvMixColumns, then XORs with rs1.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
bs selects a byte from rs2[31:0]; this instruction is defined only for RV32 and writes the result to integer rd.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «aes32dsmi a0, a1, a2, 0».
Data Protection
Understand this scenario with real code like «aes32dsmi a0, a1, a2, 0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type (OP with bs in bits 31:30).
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
bs selects the byte index (0-3) in rs2[31:0]; rs1 is the XOR source.
Middle round includes InvMixColumns; final round (aes32dsi) does not.
FAQ
Is AES32DSMI a complete algorithm implementation?
No. It performs one architecturally defined AES byte step; software still combines instructions and round keys in algorithm order.