Does AES32DSI use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES32DSI
RISC-V AES32DSI Instruction Details
Instruction ManualR-typeRV32 AES final-round byte step: select an rs2 byte, apply the inverse S-box, rotate to its byte position, and XOR with rs1.
Instruction Syntax
aes32dsi rd, rs1, rs2, bs
Syntax is rd, rs1, rs2, bs. Integer registers select x0–x31 or ABI names; bs is a two-bit byte selector, 0–3.
32-bit OP encoding: bits31:30=bs, bits29:25=10101, funct3=000, opcode=0110011.
RV32 only, requiring enabled Zknd (also included in Zkn/Zk). Shift rs2 right by bs×8, take the low byte and apply the inverse AES S-box.
Zero-extend the inverse S-box result to 32 bits, rotate left by bs×8, XOR with pre-execution rs1 and write rd; no InvMixColumns.
x0 sources are zero and rd=x0 discards writeback; overlapping operands use one pre-execution value. This instruction must have data-independent execution latency.
ZkndCrypto & Security
Related Search Terms
Instruction Behavior
aes32dsi is an RV32-only Zknd AES final-round decrypt instruction. It selects rs2[31:0] byte bs, applies the inverse S-box, rotates the 32-bit result left by bs*8, XORs rs1[31:0], and writes rd. It omits InvMixColumns.
AES32DSI Decode And Execute Animation
RV32 AES final-round decryption: byte selection, inverse SBox, rotation, XOR, and integer-register writeback.
aes32dsi
Execution Context
XLEN is fixed at 32; assumes Zknd and successful fetch. Source values are 0..0xFFFFFFFF; bs is 0–3. x0 sources must be zero and overlapping sources must agree.
31..30
29..25
24..20
19..15
14..12
11..7
6..0
01
bs
10101
fixed
01100
rs2
01011
rs1
000
funct3
01010
rd
0110011
opcode
Execution Data Path
rs1[31:0]
0x11223344
rs2[31:0]
0xA1B2C3D4
si
0xC3
InvSBox(si)
0x33
rol32(so, shamt)
0x00003300
Current Step
Decode AES32 fixed fields and bs
AES32DSI is defined only for RV32: bits 31..30 are bs; the remaining fixed fields, two integer sources, and rd identify this OP encoding.
encoding: 0x6AC58533
syntax: aes32dsi a0(x10), a1(x11), a2(x12), 1
syntax: aes32dsi a0(x10), a1(x11), a2(x12), 1
Architectural Result
a0(x10) = unspecified initial value
This animation shows only official ISA fields and state, not a particular CPU pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
RV32-only AES32DSI selects one rs2 byte using bs, applies the inverse AES S-box, zero-extends it to 32 bits, rotates left by bs×8, then XORs with rs1 into rd.
bs is 0–3: select an rs2 byte, apply the inverse AES S-box, rotate its zero-extended 32-bit result left by bs×8, then XOR with rs1; no InvMixColumns.
Operands use integer X registers; AES32DSI must have execution latency independent of operand data values.
bs selects a byte from rs2[31:0]; this RV32-only instruction writes the 32-bit result to integer rd.
Common Usage Scenarios
Crypto & Security
RV32 Zknd, a1=0x11223344, a2=0xA1B2C3D4, bs=0: select 0xD4, inverse-S-box to 0x19, rotate by 0, and write a0=0x1122335D. This is one byte-combination step.
Data Protection
RV32 Zknd, a1=0x11223344, a2=0xA1B2C3D4, bs=0: select 0xD4, inverse-S-box to 0x19, rotate by 0, and write a0=0x1122335D. This is one byte-combination step.
Pre-Use Checklist
Syntax Check
- Syntax is rd, rs1, rs2, bs. Integer registers select x0–x31 or ABI names; bs is a two-bit byte selector, 0–3.
- 32-bit OP encoding: bits31:30=bs, bits29:25=10101, funct3=000, opcode=0110011.
Semantic Check
- RV32 only, requiring enabled Zknd (also included in Zkn/Zk). Shift rs2 right by bs×8, take the low byte and apply the inverse AES S-box.
- Zero-extend the inverse S-box result to 32 bits, rotate left by bs×8, XOR with pre-execution rs1 and write rd; no InvMixColumns.
- x0 sources are zero and rd=x0 discards writeback; overlapping operands use one pre-execution value. This instruction must have data-independent execution latency.
Pitfalls / Common Confusions
bs selects the byte index (0-3) in rs2[31:0]; rs1 is the XOR source.
Final round only: does not perform InvMixColumns. Use aes32dsmi for middle rounds.
This instruction is defined only for RV32; do not treat it as an RV64 AES instruction.
FAQ
Is AES32DSI a complete algorithm implementation?
No. It processes one byte of rs2 selected by bs and combines it with rs1; it does not execute a complete AES decryption round or algorithm.