Does AES32DSI use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES32DSI
RISC-V AES32DSI Instruction Details
Instruction ManualR-typeAES final-round decrypt byte step: select a byte from rs2 by bs, apply InvSubBytes, XOR with rs1
Instruction Syntax
aes32dsi rd, rs1, rs2, bs
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZkndCrypto & Security
Related Search Terms
Instruction Behavior
aes32dsi is an RV32-only Zknd AES final-round decrypt instruction. It selects rs2[31:0] byte bs, applies the inverse S-box, rotates the 32-bit result left by bs*8, XORs rs1[31:0], and writes rd. It omits InvMixColumns.
AES32DSI Decode And Execute Animation
RV32 AES final-round decryption: byte selection, inverse SBox, rotation, XOR, and integer-register writeback.
aes32dsi
Execution Context
XLEN is fixed at 32; AES32DSI has no RV64 form.
byte select
fixed
source
xor source
fixed
destination
OP
31..30
bs=01
29..25
10101
24..20
rs2=x12
19..15
rs1=x11
14..12
000
11..7
rd=x10
6..0
0110011
Execution Data Path
rs1[31:0]
0x11223344
rs2[31:0]
0xA1B2C3D4
si
0xC3
aes_sbox_inv(si)
0x33
rol32(so, shamt)
0x00003300
Current Step
Decode AES32 fixed fields and bs
AES32DSI is defined only for RV32: bits 31..30 are bs; the remaining fixed fields, two integer sources, and rd identify this OP encoding.
encoding: 0x6AC58533
syntax: aes32dsi a0(x10), a1(x11), a2(x12), 1
syntax: aes32dsi a0(x10), a1(x11), a2(x12), 1
Architectural Result
a0(x10) = 0x11220044
This animation shows only official ISA fields and state, not a particular CPU pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
AES32DSI is a Zknd scalar cryptography instruction for AES final-round decrypt byte step. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
It selects one byte from rs2 using bs, applies the inverse AES S-box, then XORs with rs1; it does not include InvMixColumns.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
bs selects a byte from rs2[31:0]; this RV32-only instruction writes the 32-bit result to integer rd.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «aes32dsi a0, a1, a2, 0».
Data Protection
Understand this scenario with real code like «aes32dsi a0, a1, a2, 0».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
bs selects the byte index (0-3) in rs2[31:0]; rs1 is the XOR source.
Final round only: does not perform InvMixColumns. Use aes32dsmi for middle rounds.
This instruction is defined only for RV32; do not treat it as an RV64 AES instruction.
FAQ
Is AES32DSI a complete algorithm implementation?
No. It performs one architecturally defined AES half-state step; software still combines instructions and round keys in algorithm order.